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http://dx.doi.org/10.5573/JSTS.2010.10.3.193

High-Speed Low-Complexity Reed-Solomon Decoder using Pipelined Berlekamp-Massey Algorithm and Its Folded Architecture  

Park, Jeong-In (Dep. of Information and Communication Eng., Inha University)
Lee, Ki-Hoon (Dep. of Information and Communication Eng., Inha University)
Choi, Chang-Seok (Dep. of Information and Communication Eng., Inha University)
Lee, Han-Ho (Dep. of Information and Communication Eng., Inha University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.10, no.3, 2010 , pp. 193-202 More about this Journal
Abstract
This paper presents a high-speed low-complexity pipelined Reed-Solomon (RS) (255,239) decoder using pipelined reformulated inversionless Berlekamp-Massey (pRiBM) algorithm and its folded version (PF-RiBM). Also, this paper offers efficient pipelining and folding technique of the RS decoders. This architecture uses pipelined Galois-Field (GF) multipliers in the syndrome computation block, key equation solver (KES) block, Forney block, Chien search block and error correction block to enhance the clock frequency. A high-speed pipelined RS decoder based on the pRiBM algorithm and its folded version have been designed and implemented with 90-nm CMOS technology in a supply voltage of 1.1 V. The proposed RS(255,239) decoder operates at a clock frequency of 700 MHz using the pRiBM architecture and also operates at a clock frequency of 750 MHz using the PF-RiBM, respectively. The proposed architectures feature high clock frequency and low-complexity.
Keywords
Reed-Solomon codes; syndrome; key equation solver; Berlekamp-Massey algorithm; pipelined; folding; VLSI;
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