1 |
D. V. Sarwate and N. R. Shanbhag, “High-Speed
Architecture for Reed-Solomon Decoders,” IEEE
Trans. on VLSI Systems, Vol.9, No.5, pp.641-655,
Oct., 2001.
DOI
ScienceOn
|
2 |
B. Yuan, L. Li and Z. Wang, “Area-Efficient Reed-Solomon Decoder Design for 10-100Gb/s
Applications,” in Proc. IEEE Int. Symp. Circ. and
Syst. (ISCAS’2009), pp.2681-2684, May, 2009.
|
3 |
S. Lee and H. Lee, “A High-Speed Pipelined
Degree-Computationless Modified Euclidean
Algorithm Architecture for Reed-Solomon
Decoders,” IEICE Trans. on Fund. of Electronics,
Communications, and Computer Sciences,
Vol.E91-A, No.3, pp.830-835, March, 2008.
DOI
ScienceOn
|
4 |
J. H. Baek and M. H. Sunwoo, “New Degree
Computationless Modified Euclidean Algorithm
and Architecture for Reed-Solomon Decoder,”
IEEE Trans. on VLSI Systems, Vol.14, No.8,
pp.915-920, Aug., 2006.
DOI
ScienceOn
|
5 |
J. H. Baek and M. H. Sunwoo, “Enhanced degree
computationless modified Euclid’s algorithm for
Reed-Solomon decoders,” Electronics Letters-IEE,
Vol.43, No.3, pp.175-176, Feb., 2007.
DOI
ScienceOn
|
6 |
“Forward Error Correction for Submarine
Systems,” Telecommunication Standardization
Section, International Telecom. Union, ITU-T
Recommendation G.975, Oct., 2000.
|
7 |
H. M. Shao, T. K. Truong, L. J. Deutsch, J. H.
Yuen and I. S. Reed, “A VLSI Design of a Pipeline
Reed-Solomon Decoder,” IEEE Trans. on Computers,
Vol.C-34, No.5, pp.393-403, May., 1985.
DOI
ScienceOn
|
8 |
W. Wilhelm, “A New Scalable VLSI Architecture
sfor Reed-Solomon Decoders,” IEEE Jour. of
Solid-State Circuits, Vol.34, No.3, Mar., 1999.
DOI
ScienceOn
|
9 |
H. Lee, “High-Speed VLSI Architecture for Parallel
Reed-Solomon Decoder,” IEEE Trans. on VLSI
Systems, Vol.11, No.2, pp.288-294, April., 2003.
DOI
ScienceOn
|