• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.506-514
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• 1997

In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

• ETRI Journal
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• v.30 no.2
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• pp.268-274
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• 2008

This paper proposes an open-loop clock recovery circuit (CRC) using two high-Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual-mode operation. The DR filters are fabricated to obtain high Q-values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak-to-peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo-random binary sequence (PRBS) data with a word length of $2^{31}-1$ are less than 2.0 ps and 0.3 ps, respectively. The peak-to-peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error-free operation of the 40 Gb/s-class optical receiver with the dual-mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.

• Journal of Oriental Neuropsychiatry
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• v.12 no.2
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• pp.185-191
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• 2001

Objectives: This study aimed to evaluate the usefulness as a screening test of Clock Drawing Test(CDT) compared with the standard K-DRS in probably dementia. Methods: The subjects for this study consisted of 19 elderly persons who visited to the outpatient department of Oriental Neuropsychiatry of the Kyunghee Oriental hospital. They received the K-DRS and the Clock Drawing Test. Three observers evaluated them with circle, numbers, hands. Inter-rater reliability of scores from Clock Drawing Test was assessed and Pearson correlation coefficients were used to examined the relationships between scores from Clock Drawing Test and K-DRS. Results: Correlations between individual raters was highly significant (r= .957, .974, and .970, respectively: p<.001). There was stastically significant correlations between K-DRS and CDT scores (r= 0.849, p<.001). Conclusions: The CDT can be rated reliably by observers and correlations between CDT and K-DRS is significantly high. We confirmed the usefulness of CDT as simple, easily administered, low cost, and reliable general screening test for dementia.

• Journal of Satellite, Information and Communications
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• v.10 no.2
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• pp.102-108
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• 2015

In general, two way satellite communication systems based on TDMA(Time Division Multiple Access) require network clock synchronization between hub station and remote terminals. This paper describes basic concepts for network clock synchronization based on NCR(Network Clock Reference) clock recovery scheme as suggested in DVB-S2/ RCS2 international standards. in addition, a new NCR insertion method has been proposed and evaluated in terms of supporting CCM mode as well as ACM mode which optimizes throughput by changing code rates and modulation types ranging from QPSK to 32-APSK.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.82-86
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• 2009

This work is design of clock and data recovery circuit using system clock. This circuit is composed by PLL(Phase Locked Loop) to make system clock and data recovery circuit. The data recovery circuit using 1/4-rate phase picking Detector helps to reduce clock frequency. It is advantageous for high speed PLL. It can achieve a low jitter operation. The designed CDR(Clock and data recovery) has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and an active area $1{\times}1mm^2$.

• Journal of Positioning, Navigation, and Timing
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• v.5 no.3
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• pp.157-163
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• 2016

Clocks for time synchronization using radio signals such as global navigation satellite system (GNSS) may lose reference signals by intentional or unintentional jamming. This is called as holdover. When holdover occurs, a clock goes into free run in which synchronization performance is degraded considerably. In order to maintain the required precise time synchronization during holdover, accurate estimation on main parameters such as frequency offset and frequency drift is needed. It is necessary to implement an optimum filter through various simulation tests by creating clock noise in accordance with given specifications in order to estimate the main parameters accurately. In this paper, a method that creates clock noise in accordance with given specifications is described.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.2
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• pp.327-332
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• 2012

In this paper, we analyzed the influence of different observation stations distributions on satellite clock offset estimation based on the PANDA software. The result shows that, when the distance between stations is shorter than 200km, the correlation of troposphere parameter and satellite clock offset parameter is strong, the accuracy of satellite clock offset estimation will be up to 0.8ns; when the distance between stations is up to 500km, as the correction of troposphere parameter and satellite clock offset parameter is significantly reduced, and the two kinds of parameters can be distinguished.

• Molecules and Cells
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• v.22 no.3
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• pp.285-290
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• 2006

The light sensing system in the eye directly affects the circadian oscillator in the mammalian suprachiasmatic nucleus (SCN). To investigate this relationship in the rat, we examined the circadian expression of clock genes in the SCN and eye tissue during a 24 h day/night cycle. In the SCN, rPer1 and rPer2 mRNAs were expressed in a clear circadian rhythm like rCry1 and rCry2 mRNAs, whereas the level of BMAL1 and CLOCK mRNAs decreased during the day and increased during the night with a relatively low amplitude. It seems that the clock genes of the SCN may function in response to a master clock oscillation in the rat. In the eye, the rCry1 and rCry2 were expressed in a circadian rhythm with an increase during subjective day and a decrease during subjective night. However, the expression of Opn4 mRNA did not exhibit a clear circadian pattern, although its expression was higher in daytime than at night. This suggests that cryptochromes located in the eye, rather than melanopsin, are the major photoreceptive system for synchronizing the circadian rhythm of the SCN in the rat.