1 |
Rainer Kreienkamp, Hubert Siedhoff, et al., "A 10-Gb/s CMOS clock and data recovery with an analog phase interpolator," IEEE J. of Solid-State Circuits, no. 3, Mar. 2005.
|
2 |
VESA, "DisplayPort 1.1a Standard," Jan. 11, 2008.
|
3 |
www.hdmi.org "HDMI Specification 1.3a"
|
4 |
T. Palkert, "A review of current standards activite s for high speed physical layers," Proc. 5th Internatio nal Workshop on System-on-Chip for Real-Time Ap plications, pp. 495-499, July 2005.
|
5 |
Fuji Yang, Joseph Othmer, et al., "A CMOS low-power multiple 2.5-3.125Gb/s serial link macrocell for high IO bandwidth network ICs," IEEE J. of Solid-S tate Circuits, Vol.37, no. 12, Dec. 2002.
|
6 |
Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S. G. and Beomsup Kim "A Four-Channel 3.125-Gb/s/ch CMOS Serial-Link Transceiver With a Mixed-Mode Adaptive Equalizer," IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 2, FEBRUARY 2005
|