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http://dx.doi.org/10.5370/KIEE.2011.60.2.455

Design of 1/4-rate Clock and Date Recovery Circuit for High-speed Serial Display Interface  

Jung, Ki-Sang (전북대학교 전자정보공학부)
Kim, Kang-Jik (전북대학교 전자정보공학부)
Cho, Seong-Ik (전북대학교 전자공학부)
Publication Information
The Transactions of The Korean Institute of Electrical Engineers / v.60, no.2, 2011 , pp. 455-458 More about this Journal
Abstract
4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.
Keywords
Clock and Date Recovery(CDR); 1/4-rate; SERDES; High-speed serial display interface;
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