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Clock and Date Recovery Circuit Using 1/4-rate Phase Picking Detector  

Jung, Ki-Sang (Division of Electronics and Information Engineering, Chonbuk University)
Kim, Kang-Jik (Division of Electronics and Information Engineering, Chonbuk University)
Cho, Seong-Ik (Division of Electronics and Information Engineering, Chonbuk University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.46, no.1, 2009 , pp. 82-86 More about this Journal
Abstract
This work is design of clock and data recovery circuit using system clock. This circuit is composed by PLL(Phase Locked Loop) to make system clock and data recovery circuit. The data recovery circuit using 1/4-rate phase picking Detector helps to reduce clock frequency. It is advantageous for high speed PLL. It can achieve a low jitter operation. The designed CDR(Clock and data recovery) has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and an active area $1{\times}1mm^2$.
Keywords
클록 데이터 복원회로(CDR);1/4-rate 위상검출기;위상 선택방식;Low 지터;
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  • Reference
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