• Journal of Power System Engineering
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• v.6 no.3
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• pp.64-70
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• 2002

A fast decoupled algorithm for time domain simulation of power electronics circuits is presented. The circuits can be arbitrarily configured and can incorporate feedback amplifier circuits. This simulation algorithm is performed for the input series output parallel connected 2 switch forward converter. Steady state and large signal transient responses due to a step load change are simulated. The simulation results are verified through experiments.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1516-1520
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• 1987

This paper proposes fault simulation algorithms for Domino CMOS circuits, The inputs having fanouts are described correctly in the algorithms by modeling the functional block in the Domino CMOS circuits as Modified dependency matrix. The proposed algorithms generate easily the test sequence which can detect the s-a-O, s-a-I, stuckopen faults in the Domino CMOS circuits.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.823-826
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• 1998

This paper addresses a characterization of fault effects in asynchronous circuits. A characterization has been performed on races caused by a single stuck-at faults (SSAF). The faults sometimes lead to races in faulty circuits, which prevent faults from observing and the circuit is insufficiently tested. To identify those obstacles, we have proposed non-detectable single stuck-at fault(NDSSAF) conditions and proposed an algorithm to find them. In the help of the proposed methodology, the asynchronous circuits can be fully SSAF testable.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.75.1-75
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• 2002

Several model order reduction methods for large RLC circuits have been developed in the last few years. Krylop subspace based methods are extremely effective for generating the low order models of large system but there is no optimal theory for the resulting models. Alternatively, methods based truncated balanced realization have an optimality property but are too computationally expensive to use on complicated problems such as large RLC circuits. In this paper, we present a method for improving time domain response of reduced order RLC circuits. The method used here is based on combing Krylop subspace based method and truncated balanced realization method plus residualization. The metho...

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.4
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• pp.24-32
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• 1985

This paper presents the design method for multivalued logic functions using $I^2L$ circuits. First, the a비orithm that transforms delta functions into discrete functions of a truncated difference is obtained. The realization of multivalued logic circuits by this algorithm is discussed. And then, the design method is achieved by mixing discrete functions and delta functions using the modified algorithm for given multivalued truth tables. The techniques discussed here are easily extended to multi-input and multi-output logic circuits.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.3
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• pp.226-232
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• 2002

This paper explains a technique to improve the fault coverage of oscillation-test [1-5] for linear analog circuits. The transient behavior of the virtual ground is monitored during oscillation to extract information of the circuit. The limitation of the oscillation-test is analyzed, and an efficient signature analysis technique is proposed to maximize the fault coverage. The experimental result proves that the parametric fault coverage can be significantly increased by the proposed technique.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.7
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• pp.86-98
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• 1996

Modulation and demodualtion circuits of chaos frequency shift keying have been implemented using chua's circuits. The modulatin circuit, which is designed ot perform the frequency-doubling by coupled synchronization wihtout changing the intrinsic characteristics of its two chaos signals generated, modulates the digital input signals. The demodulation circuit detects the digital input signals form carrier by drive synchronization. these circuits, which are simplest until now and have no restriction to their digital input amplitudes, perform the aimed functions.

• Proceedings of the IEEK Conference
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• 2001.06e
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• pp.181-184
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• 2001

This paper has been studied driving circuits in electrical valves. Also in this paper, opto-couplers of driving circuit are replaced with digital one chip of Altera company. Designs in order to realization of one chip are carried out with Altera Max Plus II. For compact size and light weight, the realization with one chip is necessary in the electrical valves. This paper has designed and presented the digital schemetic circuits, finally the driving circuits are sucessfully operated with the designed chip and showed the saving of area in the driving circuits of electric valves.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.2
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• pp.47-55
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• 1984

This paper is concerned with a computer-aided state assignment, that is, coding race-free internal states of asynchronous sequential circuits, and a method for minimizing the combinational network of asynchronous sequential circuits. The FORTRAN version of the peoposed algorithm results in race-free state assignments and reduction of the number of connections and gates with near minimal hardware cost. Some examples are designed by the proposed computer program to illustrate the algorithm in this paper. Finally, results are compared with those of the other methods.

• Journal of the Korean Society of Industry Convergence
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• v.4 no.2
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• pp.199-205
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• 2001

With the growth of BiCMOS technology in ASIC design, the issue of analyzing fault characteristics and testing techniques for BiCMOS circuits become more important In this paper, we analyze the fault models and characteristics of high speed full-swing BiCMOS circuits and the DFT technique to enhance the testability of full-swing high speed BiCMOS circuits is discussed. The SPICE simulation is used to analyze faults characteristics and to confirm the validity of DFT technique.