• 대한전자공학회논문지SD
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• 제45권6호
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• pp.60-67
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• 2008

본 논문에서는 Bluetooth, Zigbee, WLAN 등 2.4GHz 대역 ISM-band 응용 분야를 위한 저 전력 주파수 합성기를 설계하였다. 저 전력 특성을 얻기 위해 전류소모가 큰 VCO, prescaler, ${\Sigma}-{\Delta}$ modulator 등의 전력소모를 최적화하는데 중점을 두고 설계하였다. VCO는 전력소모 측면에서 유리한 NP-core 유형의 구조를 선택하여 위상잡음 특성과 전력소모를 최적화하였으며, prescaler는 정적 전류소모가 거의 없는 동적 회로 기술이 적용된 D-F/F을 사용하여 전력소모를 줄였다. 또한 다수의 로직으로 구성되는 3차 ${\Sigma}-{\Delta}$ modulator는 'mapping circuit'으로 구조를 단순화하여 작은 면적과 저 전력소모 특성을 갖도록 하였다. $0.18{\mu}m$ CMOS 공정으로 IC를 제작하여 성능을 측정한 결과 설계된 주파수 합성기는 1.8V 전원전압에서 7.9mA의 전류를 소모하고, 100kHz offset에서 -96dBc/Hz, 1MHz offset에서 -118dBc/Hz의 위상 잡음 특성을 보였다 또한 spur 잡음 특성은 -70dBc이며, 25MHz step의 주파수 변화에 따른 위상 고정 시간은 약 $15{\mu}s$이다. 설계된 회로의 칩 면적은 pad를 포함하여 $1.16mm^2$이며 pad를 제외한 면적은 $0.64mm^2$이다.

• ETRI Journal
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• 제26권6호
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• pp.589-596
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• 2004

Packaging technologies for a broadband and narrowband modulator with a traveling wave electro-absorption modulator (TWEAM) device were developed. In developing a broadband modulator, the effects of the device and packaging designs on the broadband performance were investigated. The optimized designs were obtained through a simulation with the result that we developed a broadband modulator with a 3 dB bandwidth of 38 GHz in the electrical-to-optical (E/O) response, an electrical return loss of less than -10 dB at up to 26 GHz, an rms jitter of 1.832 ps, and an extinction ratio of 5.38 dB in a 40 Gbps non-return to zero (NRZ) eye diagram. For analog application, the effect of the RF termination scheme on the fractional bandwidth was studied. The microstrip line with a double stub as a matching circuit and a laser trimming process were used to obtain an $S_{11}$ of -34.58 dB at 40 GHz and 2.9 GHz bandwidth of less than -15 dB.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2011년도 정기총회 및 추계학술대회 논문집
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• pp.1832-1837
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• 2011

This paper presents the optimal permanent magnet shape on the rotor of an interior permanent magnet motor to reduce the core losses and improve the performance. As permanent magnet has conductivity inherently, it causes huge amount of eddy current losses by the slot harmonics with concentrated winding. This loss is roughly 100 times larger than that of distributed winding in high speed operation and it cannot be ignored, especially on traction motors. Each eddy current loss on permanent magnet has been investigated in detail by using FEM(Finite Element Method) instead of EMCNM(Equivalent Magnetic Circuit Network Method) in order to consider saturation and non-linear magnetic property. Simulation-based DOE(Design Of Experiment) is also applied to avoid large number of analyses according to each design parameter and consider expected interactions among parameters. Consequently, the optimal design to reduce the core loss on the permanent magnet while maintaining or improving motor performance is proposed by an optimization algorithm using regression equation derived and lastly, the core loss reduction on the proposed shape of the permanent magnet is verified by FEM.

• 한국산학기술학회논문지
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• 제15권7호
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• pp.4489-4493
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• 2014

LED 조명 구동장치는 150W 이상에서 효율과 발열문제가 있고 W(와트)수가 다른 조명기기를 교체하는데 불편함이 있다. 본 논문에서는 멀티채널 LED 조명 구동장치를 드라이버 연동형 구조의 전원시스템과 멀티채널 구조형태의 드라이버 회로내장형으로 설계하였다. 본 개발품은 전원효율 93% 이상 및 역율 0.98 이상의 자동 제어 컨버터 구조로써 드라이버 연동형 구조의 고효율 LED 조명 구동장치와 자기보상방식의 자기최적화 구조의 드라이버다. 따라서, 본 논문은 THD 10% 이하와 기존 컨버터 대비 중량이 40% 이상 감소하였다.

• 대한전자공학회논문지SD
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• 제42권1호
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• pp.19-24
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• 2005

본 논문에서는 압저항 효과를 이용한 Si 압력센서 제작을 최적화하였다. Si 압저항형 압력센서의 제작공정에 있어서 압저항과 알루미늄 회로 패턴 이후에 Si 이방성 식각을 통하여 수율이 개선되었다. 압저항의 위치와 공정 파라메터는 각각 ANSYS와 SUPREME 시뮬레이터를 이용하여 결정하였다. Boron-depth 프로파일 측정으로부터 p-형 Si 압저항의 두께를 측정한 결과 SUPREME 시뮬레이션으로부터 얻은 결과와 잘 부합하였다. 다이아프램을 위한 Si 이방성 식각 공정은 암모늄 첨가제 AP(Ammonium persulfate)를 TMAH(Tetra-methyl ammonium hydroxide) 용액에 첨가함으로써 최적화되었다.

• 대한전자공학회논문지SD
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• 제44권11호
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• pp.119-126
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• 2007

본 논문은 CMOS 디지털 회로에서 delay에 영향을 미치는 crosstalk을 gate의 downsizing이나 upsizing으로 발생을 회피하기 위한 효율적인 휴리스틱 알고리즘을 제시한다. 제안된 알고리즘은 게이트 사이징을 2가지 step으로 분류하며 avoidance 효과를 극대화하기 위해서 step1에서는 downsizing, step2에서는 upsizing을 순차적으로 적용하여 critical path에 인접하는 aggressor들을 차례로 회피해 나간다. 제시된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 효율성을 검증 하였으며 실험 결과는 평균적으로 8.64%의 Crosstalk Avoidance 효과를 보여줬다. 이 결과로 제시된 새로운 알고리즘의 가능성을 입증하였다.

• Current Photovoltaic Research
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• 제4권1호
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• pp.1-7
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• 2016

Among the various types of solar cells, silicon based two terminal tandem solar cell is one of the most popular one. It is designed to split the absorption of incident AM1.5 solar radiation among two of its component cells, thereby widening the wavelength range of external quantum efficiency (EQE) spectra of the device, in comparison to that of a single junction solar cell. In order to improve the EQE spectra further and raise short circuit current density ($J_{sc}$) an optimization of the tradeoff between the top and bottom cell is needed. In an optimized cell structure, the $J_{sc}$ and hence efficiency of the device can further be enhanced with the help of light trapping scheme. This can be achieved by texturing front and back surface as well as a back reflector of the device. In this brief review we highlight the development of light trapping in the silicon based tandem solar cell.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• Journal of Power Electronics
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• 제17권2호
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• pp.411-421
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• 2017

An approach based on a 2D lumped model is presented to quantify the voltage transfer gain (VTG) in power converter low power planes. The advantage of the modeling approach is the ease with which typical noise reduction devices such as decoupling capacitors or ferrite beads can be integrated into the model. This feature is enforced by a new modular approach based on effective matrix partitioning, which is presented in the paper. This partitioning is used to decouple power plane equations from external device impedance, which avoids the need for rewriting of a whole set of equation at every change. The model is quickly solved in the frequency domain, which is well suited for an automated layout optimization algorithm. Using frequency domain modeling also allows the integration of frequency-dependent devices such inductors and capacitors, which are required for realistic computation results. In order to check the precision of the modeling approach, VTGs for several layout configurations are computed and compared with experimental measurements based on scattering parameters.

• ETRI Journal
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• 제39권4호
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.