Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Timing Window Shifting by Gate Sizing for Crosstalk Avoidance

크로스톡 회피를 위한 게이트 사이징을 이용한 타이밍 윈도우 이동

  • Zang, Na-Eun (Department of Computer Science and Egineering, Sogang University) ;
  • Kim, Ju-Ho (Department of Computer Science and Egineering, Sogang University)
  • 장나은 (서강대학교 컴퓨터공학과) ;
  • 김주호 (서강대학교 컴퓨터공학과)
  • Published : 2007.11.25
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Abstract

This paper presents an efficient heuristic algorithm to avoid crosstalk which effects to delay of CMOS digital circuit by downsizing and upsizing of Gate. The proposed algorithm divide into two step, step1 performs downsizing of gate, step2 performs upsizing, so that avoid adjacent aggressor to critical path in series. The proposed algorithm has been verified on LGSynth91 benchmark circuits and Experimental results show an average 8.64% Crosstalk Avoidance effect. This result proved new potential of proposed algorithm.

본 논문은 CMOS 디지털 회로에서 delay에 영향을 미치는 crosstalk을 gate의 downsizing이나 upsizing으로 발생을 회피하기 위한 효율적인 휴리스틱 알고리즘을 제시한다. 제안된 알고리즘은 게이트 사이징을 2가지 step으로 분류하며 avoidance 효과를 극대화하기 위해서 step1에서는 downsizing, step2에서는 upsizing을 순차적으로 적용하여 critical path에 인접하는 aggressor들을 차례로 회피해 나간다. 제시된 알고리즘은 LGSynth91 벤치마크 회로에 대한 테스트 결과 효율성을 검증 하였으며 실험 결과는 평균적으로 8.64%의 Crosstalk Avoidance 효과를 보여줬다. 이 결과로 제시된 새로운 알고리즘의 가능성을 입증하였다.

Keywords

References

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