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Timing Window Shifting by Gate Sizing for Crosstalk Avoidance  

Zang, Na-Eun (Department of Computer Science and Egineering, Sogang University)
Kim, Ju-Ho (Department of Computer Science and Egineering, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.11, 2007 , pp. 119-126 More about this Journal
Abstract
This paper presents an efficient heuristic algorithm to avoid crosstalk which effects to delay of CMOS digital circuit by downsizing and upsizing of Gate. The proposed algorithm divide into two step, step1 performs downsizing of gate, step2 performs upsizing, so that avoid adjacent aggressor to critical path in series. The proposed algorithm has been verified on LGSynth91 benchmark circuits and Experimental results show an average 8.64% Crosstalk Avoidance effect. This result proved new potential of proposed algorithm.
Keywords
crosstalk; optimization; timing; analysis; estimation;
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