Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems |
Oh, Myeong-Hoon
(SW & Contents Research Laboratory, ETRI and the Department of Computer Software, University of Science and Technology (UST))
Kim, Young Woo (SW & Contents Research Laboratory, ETRI and the Department of Computer Software, University of Science and Technology (UST)) Kim, Hag Young (SW & Contents Research Laboratory, ETRI) Kim, Young-Kyun (SW & Contents Research Laboratory, ETRI) Kim, Jin-Sung (Department of Electronic Engineering, Sun Moon University) |
1 | M.H. Oh et al., "Architectural Design Issues on a Clockless 32-bit Processor Using an Asynchronous HDL," ETRI J., vol. 35, no. 3, June 2013, pp. 480-490. DOI |
2 | J. Sparso and S.B. Furber, Principles of Asynchronous Circuit Design: A System Perspective, Dordrecht, Netherlands: Kluwer Academic Publishers, 2001. |
3 | W.F. McLaughlin, A. Mitra, and S.M. Nowick, "Asynchronous Protocol Converters for Two-Phase Delay- Insensitive Global Communication," IEEE Trans. VLSI Syst., vol. 17, no. 7, July 2009, pp. 923-928. DOI |
4 | J. Kim, K. Choi, and G. Loh, "Exploiting New Interconnect Technologies in On-chip Communication," IEEE J. Emerg. Select. Topics Circuits Syst., vol. 2, no. 2, June 2012, pp. 124-136. DOI |
5 | C.A. Zeferino et al., "Models for Communication Tradeoffs on System-on-Chip," in Proc. Intell. Workshop IPBased SoC Des., Oct. 2002, p. 394. |
6 | C.T. Hsieh and M. Pedram, "Architectural Energy Optimization by Bus Splitting," IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., vol. 21, no. 4, Apr. 2002, pp. 408-414. DOI |
7 | T. Seceleanu, J. Plosila, and P. Liljeberg, "On-chip Segmented Bus: A Self-Timed Approach," in Annu. IEEE Int. ASIC/SOC Conf., Rochester, NY, USA, Sept. 25-27, 2002, pp. 216-221. |
8 | J. Lee and H.-J. Lee, "Wire Optimization for Multimedia Soc and SiP Designs," IEEE Trans. Circuits Syst. I: Regular Paper, vol. 55, no. 8, Sept. 2008, pp. 2202-2215. DOI |
9 | J. Lee, H.-J. Lee, and C. Lee, "A Phase-Based Approach for On-chip Bus Architecture Optimization," Comput. J., vol. 52, no. 6, Aug. 2009, pp. 626-645. DOI |
10 | M.H. Oh and S.W. Kim, "Asynchronous 2-Phase Protocol Based on Ternary Encoding for On-chip Interconnect," ETRI J., vol. 33, no. 5, Oct. 2011, pp. 822-825. DOI |
11 | E. Nigussie, J. Plosila, and J. Isoaho, "High-Speed Completion Detection for Current Sensing On-chip Interconnects," Electron. Lett., vol. 45, no. 11, May 2009, pp. 547-548. DOI |
12 | E. Nigussie, J. Plosila, and J. Isoaho, "Area Efficient Delay- Insensitive and Differential Current Sensing On-chip Interconnect," IEEE Int. SoC Conf., Newport Beach, CA, USA, Sept. 17-20, 2008, pp. 143-146. |
13 | M.E. Dean, T.E. Williams, and D.L. Dill, "Efficient Self- Timing with Level-Encoded 2-Phase Dual-Rail (LEDR)," Proc. Univ, California/Santa Cruz Conf. Adv. Res. VLSI, Santa Cruz, CA, USA, 1991, pp. 55-70. |
14 | E.-J. Choi, K.-R. Cho, and J.-H. Lee, "New Data Encoding Method with a Multi-value Logic for Low Power Asynchronous Circuit Design," Int. Symp. Multiple-Valued Logic (ISMVL'06), Singapore, May 2006, pp. 4. |
15 | E. Nigussie et al., "High Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling," J. VLSI Des., 2007, p. 13. |
16 | T. Takahashi and T. Hanyu, "Implementation of a High- Speed Asynchronous Data-Transfer Chip Based on Multiple-valued Current Signal Multiplexing," IEICE Trans. Electron., vol. E89-C, no. 11, Nov. 2006, pp. 1598-1604. DOI |
17 | CNU-IDEC cell library data book, IDEC Chungnam National University, 1999. |
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