• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.8
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• pp.62-71
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• 1994

A novel semiconductor device is proposed to be used as a processing element for the implementation of pulse-mode neural networks which consists of alternating n' GaAs quantum wells and undoped AlGaAs barriers sandwitched between n' GaAs cathode and P' GaAs anode and in simple circuit in conjunction with a parallel capacitive and resistive load the trigger circuit generates neuron-like pulse train output mimicking the function of axon hillock of biological neuron. It showed the sigmoidal relationship between the frequency of the pulse-train and the applied input DC voltage. In conjunction with MQWIMD the various neural circuits are proposed especially a neural chip monolithically integrated with photodetectors in order to perfrom the pattern recognition.

• Proceedings of the KIEE Conference
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• 2001.07d
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• pp.2039-2041
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• 2001

According to the deregulation of governments in the world, the power industries of United State and European nations are proceeding remote meter reading and remote load control. But the core technology of multifunctional electronic meter implemented by programmable one-chip IC, which can be the right answer of ail the power industy's efforts is now still under development in the advanced countries. Implementation of smallest size, lowest price three-phase meter with features which enable distribution automation such as bidirectional communication. The three phase metering IC and meter can be used as metering, automatic meter reading and transformer monitoring. Prepayment billing system.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.86-88
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• 2019

본 논문에서는 고주파수 구동 및 고전력밀도 아답터의 경부하 효율 개선을 위한 One Chip 디지털 통합제어 알고리즘을 제안한다. 제안 회로는 CRM PFC Boost 컨버터와 3-Level LLC 공진형 컨버터를 하나의 소형 MCU로 구성된 디지털 제어기를 사용함으로써 고주파수 구동을 가능케 하며, 주파수 제한 및 Burst mode로 구성된 알고리즘을 통해 높은 스위칭 주파수로 인해 발생하는 경부하 시 효율 개선을 통해 수동 소자와 제어단 부피 저감으로 고 전력밀도 달성이 가능하다. 최종적으로 제안 회로의 타당성 검증을 위하여 200W급 아답터의 전원회로를 위한 시작품을 제작하여 고찰된 실험결과를 제안한다.

• Journal of Semiconductor Engineering
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• v.3 no.1
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• pp.154-160
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• 2022

In this paper, we design a DC-DC boost converter with RF noise immunity to supply a stable positive output voltage for OLED displays. For RF noise immunity, an input voltage variation reduction circuit (IVVRC) is adopted to ensure display quality by reducing the undershoot and overshoot of output voltage. The boost converter for a positive voltage Vpos operates in the SPWM-PWM dual mode and has a dead-time controller using a dead-time detector, resulting in increased power efficiency. A chip was fabricated using a 0.18 um BCDMOS process. Measurement results show that power efficiency is 30% ~ 76% for load current range from 1 mA to 100 mA. The boost converter with the IVVRC has an overshoot of 6 mV and undershoot of 4 mV compared to a boost converter without that circuit with 18 mV and 20 mV, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.63-70
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• 2013

This paper describes a high PSRR low-dropout(LDO) linear regulator for wide frequency range without output-capacitor. Owing to both of the cascode compensation technique and the current buffer compensation technique in nested Miller compensation loop, the proposed LDO not only maintaines high stability but also achieves high PSRR over wide frequency range with reasonable on-chip capacitances. Since the external capacitor is removed by the proposed compensation techniques, the cost for pad is eliminated. The designed LDO works under the input voltage range from 2.5V to 4.5V and provides up to 10mA load current with the output voltage of 1.8V. The LDO was implemented with 0.18um CMOS technology and the area is 300um X 120 um. The measured power supply rejection ratio(PSRR) is -76dB and -43dB at DC and 1MHz, respectively. The operating current is 25uA.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.5 no.5
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• pp.1049-1068
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• 2011

In this paper a simple and effective call admission control (CAC) scheme is proposed for the emerging interleave-division multiple-access (IDMA) systems, supporting a variety of traffic types and offering different quality of service (QoS) requirements and priority levels. The proposed scheme is signal-to-interference-plus-noise ratio (SINR) evolution based CAC (SE-CAC). The key idea behind the scheme is to take advantage of the SINR evolution technique in the process of making admission decisions, which is developed from the effective chip-by-chip (CBC) multi-user detection (MUD) process in IDMA systems. By virtue of this semi-analytical technique, the MUD efficiency can be estimated accurately. Additionally, the computational complexity can be considerably reduced. These features make the scheme highly suitable for IDMA systems, which can combat intra-cell interference efficiently with simple CBC MUD. Analysis and simulation results show that compared to the traditional CAC scheme considering MUD efficiency as a constant, the proposed SE-CAC scheme can guarantee high power efficiency and throughput for multimedia traffic even in heavy load conditions, illustrating the high efficiency of CBC MUD. Furthermore, based on the SINR evolution, the SE-CAC can make accurate estimation of available resource considering the effect of MUD, leading to low outage probability as well as low blocking and dropping probability.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.44-53
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• 2008

In this paper, we present the design of delta-sigma modulation-based class-D amplifier for driving headphones in portable audio applications. The presented class-D amplifier generates PWM(pulse width modulation) signals using a single-bit fourth-order high-performance delta-sigma modulator. To achieve a high SNR(signal-to-noise ratio) and ensure system stability, the locations of the modulator loop filter poles and zeros are optimized and thoroughly simulated. The test chip is fabricated using a standard $0.18{\mu}m$ CMOS process. The active area of the chip is $1.6mm^2$. It operates for the signal bandwidth from 20Hz to 20kHz. The measured THD+N(total harmonic distortion plus noise) at the $32{\Omega}$ load terminal is less than 0.03% from a 3V power supply.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.1
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• pp.35-41
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• 2002

Flip-chip interconnection that uses solder bump is an essential technology to improve the performance of micro-electronics which require higher working speed, higher density, and smaller size. In this paper, the shear strength of Cr/Cr-Cu/Cu UBM structure of the high-melting solder bump and that of low-melting solder bump after aging is evaluated. Observe intermetallic compound and bump joint condition at the interface between solder and UBM by SEM and TEM. And analyze the shear load concentrated to bump applying finite element analysis. As a result of experiment, the maximum shear strength of Sn-97wt%Pb which was treated 900 hrs aging has been decreased as 25% and Sn-37wt%Pb sample has been decreased as 20%. By the aging process, the growth of $Cu_6/Sn_5$ and $Cu_3Sn$ is ascertained. And the tendency of crack path movement that is interior of a solder to intermetallic compound interface is found.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.87-96
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• 2019

Low power issue is one of the most critical problems in the Internet of Things (IoT), which are powered by battery. To solve this problem, various approaches have been presented so far. In this paper, we propose a method to reduce the power consumption by reducing the numbers of accesses into the flash memory consuming a large amount of power for on-chip software execution. Our approach is based on using cooperative logging structure to distribute the sampling overhead in single sensor node to adjacent nodes in case of rare-event applications. The proposed algorithm to identify event occurrence is newly introduced with negative feedback method by observing difference between past data and recent data coming from the sensor. When an event with need of flash access is determined, the proposed approach only allows access to write the sampled data in flash memory. The proposed event detection algorithm (EDA) result in 30% reduction of power consumption compared to the conventional flash write scheme for all cases of event. The sampled data from the sensor is first traced into the random access memory (RAM), and write access to the flash memory is delayed until the page buffer of the on-chip flash memory controller in the micro controller unit (MCU) is full of the numbers of the traced data, thereby reducing the frequency of accessing flash memory. This technique additionally reduces power consumption by 40% compared to flash-write all data. By sharing the sampling information via LoRa channel, the overhead in sampling data is distributed, to reduce the sampling load on each node, so that the 66% reduction of total power consumption is achieved in several IoT edge nodes by removing the sampling operation of duplicated data.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1581-1587
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• 2021

As embedded system are used widely and variously, multi-edge system, which multiple edges gather and perform complex operations together, is actively operating. In a multi-edge system, it often occurs that an abnormal operation at one edge is transferred to another edge or the entire system goes down. It is necessary to determine and control edge anomalies in order to prevent system down, but this can be a heavy burden on the resource-limited edge. As a solution to this, we use power consumption data to check the state of the edge device and transmit it based on a QRcode to check and control errors at the server. The architecture proposed in this paper is implemented using 'chip-whisperer' to measure the power consumption of the edge and 'Raspberry Pi 3' to implement the server. As a result, the proposed architecture server showed successful data transmission and error determination without additional load appearing at the edge.