• 제목/요약/키워드: Chip Impedance

검색결과 190건 처리시간 0.02초

인식거리 향상을 위한 UHF 대역 RFID 태그 임피던스 정합 설계 (Impedance Tuning and Matching Characteristics of UHF RFID Tag for Increased Reading Range)

  • 이종욱;권홍일;이범선
    • 한국전자파학회:학술대회논문집
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    • 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
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    • pp.279-284
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    • 2005
  • We investigated the impedance matching characteristics of UHF-band RFID tag antenna and tag chip for increased reading range. A voltage multiplier designed using 0.4 $\mu$m zero-$V_T$ MOSFET showed that DC output voltage of about 2 V can be obtained using standard CMOS process. The input impedance of the voltage multiplier was examined to achieve impedance matching to the RFID tag antenna using analytical and numerical approaches. The input impedance of the voltage multiplier could be varied in a wide range by selecting the size of MOSFET and the number of multiplying stages, and thus can be impedance matched to a tag antenna in presence of other tag circuit blocks. A meander line inductively-coupled RFID tag antenna operating at UHF band also shows the feasibility of impedance matching to tile RFID tag chip.

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고 전도율과 고 유전율 물질에 부착 가능한 RFID 태그 안테나 (RFID Tag Antenna Mountable on High-Conductivity and High Permittivity an Materials at UHF Band)

  • 권홍일;이범선
    • 한국전자파학회논문지
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    • 제16권8호
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    • pp.797-802
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    • 2005
  • 본 논문에서는 UHF 대 역용(911 MHz) 태그로 금속체 부착 가능한 태그로써 PIFA 형태 를 채택하여, $50{\times}30{\times}4$ mm의 크기로 칩의 임피던스(77-j100 ${\Omega}$)와 공액 정합이 되는 태그 안테나를 설계 및 제작하였다. RFID 태그로부터 backscattering 되는 필드, 즉 RCS(Radar Cross Section)을 통해 태그 안테나의 성능을 평가하였다. 제안된 태그 안테나는 칩의 임피던스에 쉽게 정합시킬 수 있는 간단한 구조이고, foam을 이용하여 저가에 생산할 수 있는 장점을 가지고 있다. RCS값이 칩이 단락일 때 RCS 값은 $-21\;dBm^2$이고, 정합일 때는 $-10.2\;dBm^2$로 효율적인 RCS 특성을 가지고 있다.

DLL 보드 상에 코어 및 I/O 잡음에 의한 칩의 성능 분석 (Analysis of Chip Performance by Core and I/O SSN Noise on DLL Board)

  • 조성곤;하종찬;위재경
    • 마이크로전자및패키징학회지
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    • 제13권4호
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    • pp.9-15
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    • 2006
  • 이 논문은 코어와 I/O 회로가 포함된 PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks)의 임피던스 변화에 따른 칩의 성능 분석을 나타내었다. I/O 전원에 연결된 코어 전원 잡음이 I/O 스위칭에 어떠한 영향이 미치는지 시뮬레이션 결과를 통하여 보였다. 또한 직접 설계한 $7{\times}5$인치 DLL(Delay Locked Loop)시험 보드를 사용하여 칩의 동작 지점에 따른 전원 잡음의 효과를 분석하였다. $50{\sim}400MHz$에 주파수 대역에 따른 DLL의 지터를 측정하고 시뮬레이션 결과로 얻어진 임피던스 값과 비교하였다. PDN의 공진 피크가 100MHz 주파수에서 1옴보다 큰 임피던스를 갖기 때문에 DLL의 지터는 주파수가 100MHz 근처에서 증가함을 보여준다. 타겟 임피던스를 줄이기 위한 방법인 디커플링 커패시터에 따른 칩과 보드의 임피던스 변화를 보였다. 따라서 전원 공급망 설계는 디커플링 커패시터와 함께 코어 스위칭 전류와 I/O 스위칭 전류를 같이 고려해야 한다.

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Wideband Low-Reflection Transmission Lines for Bare Chip on Multilayer PCB

  • Ramzan, Rashad;Fritzin, Jonas;Dabrowski, Jerzy;Svensson, Christer
    • ETRI Journal
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    • 제33권3호
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    • pp.335-343
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    • 2011
  • The pad pitch of modern radio frequency integrated circuits is in the order of few tens of micrometers. Connecting a large number of high-speed I/Os to the outside world with good signal fidelity at low cost is an extremely challenging task. To cope with this requirement, we need reflection-free transmission lines from an on-chip pad to on-board SMA connectors. Such a transmission line is very hard to design due to the difference in on-chip and on-board feature size and the requirement for extremely large bandwidth. In this paper, we propose the use of narrow tracks close to chip and wide tracks away from the chip. This narrow-to-wide transition in width results in impedance discontinuity. A step change in substrate thickness is utilized to cancel the effect of the width discontinuity, thus achieving a reflection-free microstrip. To verify the concept, several microstrips were designed on multilayer FR4 PCB without any additional manufacturing steps. The TDR measurements reveal that the impedance variation is less than 3 ${\Omega}$ for a 50 ${\Omega}$ microstrip and S11 better than -9 dB for the frequency range 1 GHz to 6 GHz when the width changes from 165 ${\mu}m$ to 940 ${\mu}m$, and substrate thickness changes from 100 ${\mu}m$ to 500 ${\mu}m$.

Microfabricated Cell Chip for Cell-based in vitro Assay

  • 박제균;김태한;이상은;김수현;윤규식;이정건
    • 한국생물공학회:학술대회논문집
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    • 한국생물공학회 2000년도 추계학술발표대회 및 bio-venture fair
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    • pp.115-118
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    • 2000
  • 미세 가공 기술을 이용하여 제작된 IDA 전극을 활용하여 임피던스 측정방식의 cell chip으로의 응용에 대해 고찰하였다. IDA 전극은 기존의 반도체 공정으로서 손쉽게 제작할 수 있고, 대량 제작시 전극의 재현성 확보가 용이하고 소형화 할 수 있으며 낮은 단가로 제작될 수 있는 장점이 있다. IDA 전극을 채용한 cell chip을 B16-F1 melanoma 세포 배양에 적용한 결과, 세포성장과 임피던스 변화량이 상관성을 보였고, 세포의 성장을 저해하는 약물의 투과시 cell chip의 임피던스 변화 역시 기존의 방법과 유사한 결과를 보여 주었다.

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Solenoid 형태의 초소형 SMD RF 칩 인덕터에 대한 주파수 특성 (Frequency Characteristics for Micro-scale SMD RE Chip Inductors of Solenoid-Type)

  • 김재욱
    • 한국산학기술학회논문지
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    • 제8권3호
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    • pp.454-459
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    • 2007
  • 본 논문에서는 비정질 $Al_2O_3$ 코아 재료를 응용한 단순 solenoid 형태의 소형 고성능 RF 칩 인덕터를 연구하였다. 인덕터 크기는 $0.86{\times}0.46{\times}0.45mm^3$이고, $27{\mu}m$ 직경의 Cu를 코일로 사용하였다. RF 칩 인덕터의 인덕턴스(L), 양호 인자(Q), 임피던스(Z), 커패시턴스(C)와 등가회로 파라미터 등의 주파수 특성은 RF impedance/Material Analyzer (HP16193A test fixture가 장착된 HP4291B)로 측정되었다. $9{\sim}12$회의 권선수를 가진 RF 칩 인덕터들의 인덕턴스 값은 $21{\sim}34nH$ 범위를 가진다. 이들의 자기공진주파수(SRF)는 $5.7{\sim}3.7GHz$ 영역을 나타낸다. 또한 자기공진주파수가 증가함에 따라 인덕턴스 값이 감소하는 경향을 보이고 있다. 인덕터의 SRF는 인덕턴스가 증가함에 따라 감소하며, Q의 값은 $900MHz{\sim}1.7GHz$ 주파수 범위에서 최대 $38{\sim}49$까지 얻어졌다.

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GHz EMI Characteristics of 3D Stacked Chip PDN with Through Silicon Via (TSV) Connections

  • Pak, Jun-So;Cho, Jong-Hyun;Kim, Joo-Hee;Kim, Ki-Young;Kim, Hee-Gon;Lee, Jun-Ho;Lee, Hyung-Dong;Park, Kun-Woo;Kim, Joung-Ho
    • Journal of electromagnetic engineering and science
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    • 제11권4호
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    • pp.282-289
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    • 2011
  • GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

Bi계 ZnO 칩 바리스터의 저온소결과 전기적 특성 (Low Temperature Sintering and Electrical Properties of Bi-based ZnO Chip Varistor)

  • 홍연우;신효순;여동훈;김진호
    • 한국전기전자재료학회논문지
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    • 제24권11호
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    • pp.876-881
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    • 2011
  • The sintering, defect and grain boundary characteristics of Bi-based ZnO chip varistor (1,608 mm size) have been investigated to know the possibility of lowering a manufacturing price by using 100 % Ag inner-electrode. The samples were prepared by general multilayer chip varistor process and characterized by shrinkage, SEM, current-voltage (I-V), admittance spectroscopy (AS), impedance and modulus spectroscopy (IS & MS) measurement. There are no problems to make a chip varistor with 100% Ag inner-electrode in the sintering temperature range of 850~900$^{\circ}C$ for 1 h in air. A good varistor characteristics ($V_n$= 9.3~15.4 V, a= 23~24, $I_L$= 1.0~1.6 ${\mu}A$) were revealed but formed $Zn_i^{{\cdot}{\cdot}}$(0.209 eV) as dominant defect, and increased the distributional inhomogeneity and the temperature instability in grain boundary barriers.

ECG 원칩 솔루션의 진단용 심전계 적용을 위한 타당성 연구 (A Feasibility Study for Application of Single-Chip Solution for Diagnostic Resting ECG)

  • 강범선;최기상
    • 대한의용생체공학회:의공학회지
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    • 제36권4호
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    • pp.86-94
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    • 2015
  • In order for medical devices to be used outside hospital, they have to be not only of small size but also power consumption has to be kept at low level. This study investigates the feasibility of application of ADS1298 ECG single-chip solution developed by Texas Instruments Inc. for use in development of a new platform for diagnostic resting ECG. To prove the feasibility of commercial products based on the ADS1298 chip, the performance of the ADS1298 chip was measured in terms of input impedance, common mode rejection, frequency response, and input dynamic range using the testing method under the suitability criteria of the IEC 60601-2-25 standard. Result of the this study shows that commercialization of the ECG products based on the ADS1298 ECG single-chip solution that satisfies the international standards would be possible, if the manufactures take the filter characteristics into account in building a new platform for diagnostic resting ECG.

솔레노이드 형태의 RF 칩 인덕터에 대한 연구 (A Study for Solenoid-Type RF Chip Inductors)

  • 김재욱;윤의중;정여창;홍철호
    • 한국전기전자재료학회논문지
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    • 제13권10호
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    • pp.840-846
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    • 2000
  • In this work, small-size, high-performance solenoid-type RF chip inductors utilizing a low-loss Al$_2$O$_3$core material were investigated. The size of the chip inductors fabricated in this work were 15$\times$10$\times$0.7㎣, 2.1$\times$1.5$\times$10㎣, and 2.4$\times$2.0$\times$1.4㎣ and copper (Cu) wire with 40 ㎛ diameter was used as the coils. High frequency characteristics of the inductance, quality factor, and impedance of developed inductors were measured suing an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). It was observed that the developed inductors with the number of turns of 7 have the inductance of 33 to 100nH and exhibit the self-resonant frequency (SRF) of .26 to 1.1 GHz. The SRF of inductors decreases with increasing the inductance and the inductors have the quality factor of 60 to 80 in the frequency range of 300 MHz to 1.1 GHz. In this study, small-size solenoid-type RF chip inductors with high inductance and high quality factor were fabricated successfully. It is suggested that the thin film-type inductor is necessary to fabricate the smaller size inductors at the expence of inductance and quality factor values.

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