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http://dx.doi.org/10.4313/JKEM.2011.24.11.876

Low Temperature Sintering and Electrical Properties of Bi-based ZnO Chip Varistor  

Hong, Youn-Woo (Future Convergence Ceramic Division, Korea Institute of Ceramic Engineering and Technology)
Shin, Hyo-Soon (Future Convergence Ceramic Division, Korea Institute of Ceramic Engineering and Technology)
Yeo, Dong-Hun (Future Convergence Ceramic Division, Korea Institute of Ceramic Engineering and Technology)
Kim, Jin-Ho (School of Materials Science and Engineering, Kyungpook National University)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.24, no.11, 2011 , pp. 876-881 More about this Journal
Abstract
The sintering, defect and grain boundary characteristics of Bi-based ZnO chip varistor (1,608 mm size) have been investigated to know the possibility of lowering a manufacturing price by using 100 % Ag inner-electrode. The samples were prepared by general multilayer chip varistor process and characterized by shrinkage, SEM, current-voltage (I-V), admittance spectroscopy (AS), impedance and modulus spectroscopy (IS & MS) measurement. There are no problems to make a chip varistor with 100% Ag inner-electrode in the sintering temperature range of 850~900$^{\circ}C$ for 1 h in air. A good varistor characteristics ($V_n$= 9.3~15.4 V, a= 23~24, $I_L$= 1.0~1.6 ${\mu}A$) were revealed but formed $Zn_i^{{\cdot}{\cdot}}$(0.209 eV) as dominant defect, and increased the distributional inhomogeneity and the temperature instability in grain boundary barriers.
Keywords
ZnO chip varistor; Sintering; Electrical properties; Impedance spectroscopy;
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Times Cited By KSCI : 4  (Citation Analysis)
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