• Journal of Information Display
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• v.6 no.4
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• pp.6-10
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• 2005

The dependence of hysteresis characteristics in low temperature poly-Si (LTPS) thin film transistors (TFTs) on the gate-source voltage (Vgs) or the drain-source voltage (Vds) bias is investigated and discussed. The hysteresis levels in both p-type and n-type LTPS TFTs are independent of Vds bias but increase as the sweep range of Vgs increases. It has been found that the hysteresis in both p-type and n-type LTPS TFTs originated from charge trapping and de-trapping in the channel region rather than at the source/drain edges.

• 전기의세계
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• v.26 no.4
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• pp.68-72
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• 1977

The main purpose of this paper is to study on the nature of the traps in polymer. The polyethlene is typical of polymer material as to be selected for a sample. The current I$_{th}$ are obtained with an small external bias voltage from high density polyethylene which have been treated by the high-field application. Two peaks, P$_{1}$ and P$_{2}$ with maxima near 85.deg. C, respectively, appeared on the current I$_{th}$ spectrum. From the results of experiment, It is clear that The current I$_{th}$ arises from the drift, under the external field, of carriers released from the trap sites by the heating and the trap is surrounded by a potential barrier and trapping proceeds during the high-field treatment. The obtained results can suggest that polyethylene contains trap sites which have an important role in the electrical conduction and breakdown of polymeric materials.rials.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.367-372
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• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1438-1440
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• 1998

In this work, simultaneous measur of space charge and conduction current was c out in LDPE with air gap by Pulsed-Electro-Aco Method. Also, effect of long time charging at con electric field on the formation of space charge conduction was investigated. From the experim results. we knew that the homo space charge formed near the dielectric surfaces and moving the bulk of dielectric as the electric field elevated. This was related with the deep traps b carriers and de trapping by Poole-field lowering conduction current was coincident with the Pool emission. From the long time charging experimen obtained the results that the negative space was moving into the dielectric bulk as the cha continued and the positive space charge accumulated at upper surface of LDPE.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.372-372
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• 2014

반도체 검출기는 입사되는 X선 에너지에 의하여 이온화되어 발생하는 전자 전공쌍을 수집함으로 방사선 정보를 확인하는 선량계로써 많은 연구와 활용이 이루어지고 있다. 하지만, X선 에너지에 의하여 반도체 검출기에서 발생하는 전기적 신호량이 높지 않기 때문에 누설 전류의 저감이 필수적이다. 누설 전류를 저감시키기 위한 방안으로 반도체 층과 전극 층의 Schottky Contact 구조의 설계, Insulating Layer의 사용, 높은 비저항의 반도체 물질 연구 등이 이루어지고 있다. 하지만, 기존에 누설 전류 저감을 위하여 Insulating Layer를 전극층과 반도체 층 사이에 형성하는 연구에 있어서 Insulating Layer와 반도체 층의 계면 사이에서 발생하는 Charge Trapping으로 인하여 생성되는 신호의 Reproducibility 저하, 동영상 적용의 제한 등의 문제점을 겪어왔다. 이에 본 논문에서는 누설 전류를 저감시킴과 동시에 Charge Trapping의 최소화를 이루기 위하여 Insulating Layer의 두께 최적화 연구를 수행하였다. 본 연구에서 사용한 Insulating Layer는 검출기 표면에 입사하는 X선 정보 손실을 최소화 시키는 동시에 누설 전류와 Charge Trapping을 최소화 시키는 방법으로써 CVD방법으로 검출기 표면에 균일하게 Insulating Layer를 코팅하였다. Insulating 물질은 Parylene을 사용하였으며, 그 중 온도, 습도 등 외부환경에 영향을 적게 받는 type C를 사용하였다. 증착에 사용한 장비의 진공도는 Torr로 설정하여 증착되는 Parylene의 두께가 약 $0.3{\mu}m$가 되게 하였으며, 실험에는 반도체 물질 PbO를 사용하였다. Parylene의 절연 특성은 Dark Current와 Sensitivity를 측정한 SNR을 이용하여 Parylene코팅이 되지 않은 동일 반도체 검출기와의 신호를 비교하였으며 또한 Parylene를 다층 제작한 검출기의 수집 신호량을 비교하였다. 제작한 검출기의 X선 조사 시의 수집 전하량 측정 결과, 100 kVp, 100mA, 0.03s의 X선 조건에서 $1V/{\mu}m$의 기준 시, Parylene를 코팅하지 않은 PbO 검출기의 Dark current는 0.0501 nA/cm2, Sensitivity는 0.6422 nC/mR-cm2, SNR은 12.184이었으며, Parylene단층의 두께인 $0.3{\mu}m$로 증착된 시편의 Dark current는 0.04097 nA/cm2, Sensitivity는 0.53732 nC/mR-cm2으로 Dark current가 감소되고 sensitivity도 감소하였지만 SNR은 13.1150으로 높아진 것을 확인할 수 있었다. Perylene이 $0.6{\mu}m$로 증착된 시편의 경우, Dark Current는 0.04064 nA/cm2, Sensitivity는 0.31473 nC/mR-cm2, SNR은 7.7443으로써 Insulating Layer가 없는 시편보다 SNR이 약 40% 낮아진 것을 확인할 수 있었다. Parylene이 $0.9{\mu}m$로 증착된 시편의 경우 Dark current는 0.0378 nA/cm2, Sensitivity 0.0461 nC/mR-cm2로 Insulating Layer가 없는 시편에 비해 SNR은 약 1/12배 감소한 1.2196이었고, Parylene이 $1.2{\mu}m$로 증착된 시편의 SNR은 1.1252로서 더 감소하였다. 따라서 Parylene을 다층 코팅한 검출기일수록 절연 효과의 영향이 커짐으로써 SNR 비교 시 수집되는 신호량이 줄어드는 것을 확인하였다. 반도체 검출기의 누설 전류를 저감시킴과 동시에 신호 수집율에 영향을 최소화시키기 위하여 Insulating Layer의 두께를 적절하게 설정하여 적용하면 Insulating Layer가 없는 검출기에 비해 누설전류를 최소한으로 줄일 수 있고 신호 검출효율이 감소하는 것을 방지할 수 있을 것이라 사료된다.

• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.73-76
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• 2014

$Pt/Al_2O_3/La_2Si_5O_x/SiO_2/Si$ charge trap memory capacitors were prepared, in which the $La_2Si_5O_x$ film was used as the charge trapping layer, and the effects of post annealing atmospheres ($NH_3$ and $N_2$) on their memory characteristics were investigated. $La_2O_3$ nanocrystallites, as the storage nodes, precipitated from the amorphous $La_2Si_5O_x$ film during rapid thermal annealing. The $NH_3$ annealed memory capacitor showed higher charge storage performances than either the capacitor without annealing or the capacitor annealed in $N_2$. The memory characteristics were enhanced because more nitrogen was incorporated at the $La_2Si_5O_x/SiO_2$ interface and interfacial reaction was suppressed after the $NH_3$ annealing treatment.

• ETRI Journal
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• v.31 no.5
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• pp.604-606
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• 2009

The primary dose effects on an insulated gate bipolar transistor (IGBT) irradiated with a $^{60}Co$ gamma-ray source are found in both of the components of the threshold shifting due to oxide charge trapping in the MOS and the reduction of current gain in the bipolar transistor. In this letter, the IGBT macro-model incorporating irradiation is implemented, and the electrical characteristics are analyzed by SPICE simulation and experiments. In addition, the collector current characteristics as a function of gate emitter voltage, VGE, are compared with the model considering the radiation damage of different doses under positive biases.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1673-1676
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• 2007

We have investigated the degradation mechanism of hydrogenated amorphous silicon (a- Si:H) thin film transistors (TFTs) The threshold voltage of driving a-Si:H TFT is shifted severely by electrical bias due to a charge trapping and defect state creation. And the short channel TFTs exhibit less threshold voltage degradation than long channel TFTs. We propose the pixel circuits employing negative bias annealing scheme in order to suppression of threshold voltage shift of a-Si:H TFT.

• Proceedings of the Optical Society of Korea Conference
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• 2001.02a
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• pp.206-207
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• 2001

The photorefractive (PR) effect in liquid crystals sandwiched between photoconductive polymer layers was first studied by Ono et al. They reported that the PR effect vanished at steady state If there were not insulating layers because no charge trapping occurred in the photoconductive poly(N-vinylcarbazole) (PVK) layers. However we observed a significant PR effect in the polymer layered liquid crystal (PLLC) system where a liquid crystal layer doped with fullerene is sandwiched between two photoconductive PVK layers. (omitted)

• 전기의세계
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• v.27 no.3
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• pp.31-35
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• 1978

In this paper, in order to clarify the mature of traps in polymer, the thermally stimulated current (TSC) measurements were mad on high density polyethylene by changing the condition of the high-field treatment such as the strength of the field (Fe), the treatment time (te) and the heating rate (.betha.). In addition, the TSC measured from the HDPE was compared with that from LDPE having different crystallinity. The obtained results can suggest that the trapping proceeds during the high-field treatment and the trap associated with the peak P$_{2}$ may have the closed relation to drystallinity and the release of trapped charge is enhanced by the molecular motion.