• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.148-152
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• 2004

The direct lateral profile and retention characteristics of locally trapped-charges in the nitride layer of the two-bit polysilicon-oxide-nitride-oxide-silicon (SONOS) memory are investigated by using the charge pumping method. After charges injection at the drain junction region, the lateral diffusion of trapped charges as a function of retention time is directly shown by the results of the local threshold voltage and the trapped-charges quantities.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.894-897
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• 2006

Spatial distribution of injected electrons and holes is evaluated by using single-junction charge pumping technique in SONOS(Poly-silicon/Oxide/Nitride/Oxide/Silicon) memory cells. Injected electron are limited to length of ONO(Oxide/Nitride/oxide) region in locally ONO stacked cell, while are spread widely along with channel in fully ONO stacked cell. Hot-holes are trapped into the oxide as well as the ONO stack in locally ONO stacked cell.

• Transactions on Electrical and Electronic Materials
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• v.17 no.1
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• pp.25-28
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• 2016

We investigate the effect of interface states on the endurance of a charge trap flash (CTF) NOR array using charge pumping methods. The endurance test was completed from one cell selected randomly from 128 bit cells, where the memory window value after 10² program/erase (P/E) cycles decreased slightly from 2.2 V to 1.7 V. However, the memory window closure abruptly accelerated after 10³ P/E cycles or more (i.e. 0.97 V or 0.7 V) due to a degraded programming speed. On the other hand, the interface trap density (Nit) gradually increased from 3.13×10¹¹ cm⁻² for the initial state to 4×10¹² cm⁻² for 10² P/E cycles. Over 10³ P/E cycles, the Nit increased dramatically from 5.51×10¹² cm⁻² for 10³ P/E cycles to 5.79×10¹² cm⁻² for 10⁴ P/E cycles due to tunnel oxide damages. These results show good correlation between the interface traps and endurance degradation of CTF devices in actual flash cell arrays.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.216.2-216.2
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• 2015

본 연구에서는 charge pumping method에서 사용되는 변수들의 변화를 이용하여 hot carrier stress가 MOSFET소자의 oxide내에서의 trap 분포에 어떤 영향을 미치는지에 대해서 연구하였다. trap 분포를 확인하기 위해 스트레스 전 후에 reverse bias와 주파수에 따른 trap의 양을 측정 하였다. 스트레스 전과 후에 reverse bias와 주파수가 감소할수록 trap이 증가하는 모습이 나타났고, 스트레스 후에는 전과 비교하여 전반적으로 trap의 양이 증가하였다. 또한, 스트레스 전과 후에 MOSFET소자의 trap density는 center region에서 $2.89{\times}$10^10에서 $1.64{\times}$10^10으로 감소하였고, drain region에서 $2.83{\times}$10^10에서 $5.26{\times}$10^10으로 증가한 것을 확인하였다. 이는 reverse bias와 주파수의 가변에 따라서 trap의 공간적 분포를 측정할 수 있다는 것을 의미한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.328.1-328.1
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• 2014

MOSFET degradation의 대부분은 hot-carrier injection에 의한 interface state (Dit)의 생성에서 비롯되며 따라서 본 연구에서는 신뢰성에 대한 한 가지 방법으로 Charge pumping method를 이용하여 MOSFET의 interface trap(Dit)의 변화를 측정하였다. 소스와 드레인을 ground로 묶고 게이트에 펄스를 인가한 후 Icp를 측정하여 Dit를 추출하였다. 온도를 293~343 K까지 5 K씩 가변했을 때 293K의 Icp(${\mu}A$)는 0.12 nA 313 K는 0.112 nA 343 K는 0.926 nA이며 Dit (cm-1/eV-1)는 $1.61{\times}10^{12}$ (Cm-2/eV-1) $1.49{\times}10^{12}$ (Cm-2/eV-1) $1.23{\times}10^{12}$ (Cm-2/eV-1)이다. 측정결과 Dit는 Icp가 높은 지점에서 추출되며 온도가 높아지게 되면 Icp전류가 낮아지고 Dit가 줄어드는 것을 볼 수 있다. 온도가 올라가게 되면 carrier들이 trap 준위에서 conduction band 위쪽에 이동하게 되어서 interface에 trap되는 양이 작아지게 된다. 그래서 이때 Icp를 이용해 추출한 Dit 는 실제로 trap의 양이 줄어든 것이 아니라 Thermal excess 현상으로 인해 측정되는 Icp의 양이 줄어든 것으로 분석할 수 있다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.59-64
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• 1994

The Si-SiO$_2$interface trpas of the degraded short-channel SONOSFET memory devices were investigated using the charge pumping techniques. The degradation of devices with write/erase cycle appeared as the increase of the Si-SiO$_2$interface trap density. In order to determine the capture cross-section of the interface trap. I$\_$CP/-V$\_$GL/ characteristic curves were measured at different temperatures. Also, the spatial distributions of Si-SiO$_2$interface trap were examined by the variable-reverse bias boltage method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.137-145
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• 2008

In this paper, novel CMOS charge pump having NMOS and PMOS transfer switches and a bulk-pumping circuit has been proposed. The NMOS and PMOS transfer switches allow the charge pump to improve the current-driving capability at the output. The bulk-pumping circuit effectively solves the bulk forward problem of the charge pump. To verify the effectiveness, the proposed charge pump was designed using a 80-nm CMOS process. The comparison results indicate that the proposed charge pump enhances the current-driving capability by more than 47% with pumping speed improved by 9%, as compared to conventional charge pumps having either NMOS or PMOS transfer switch. They also indicate that the charge pump reduces the worst-case forward bias of p-type bulk by more than 24%, effectively solving the forward current problem.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.257-263
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• 2006

New charge pump circuits with low area and high power efficiency are proposed and verified in this paper. These pump circuits do not suffer the voltage stress higher than $V_{DD}$ across their pumping capacitors. Thus they can use the thin-oxide MOSFETs as the pumping capacitors. Using the thin-oxide capacitors can reduce the area of charge pumps greatly while keeping their driving capability. Comparing the new pump (NCP-2) with the conventional pump circuit using the thick-oxide capacitors shows that the power efficiency of NCP-2 is the same with the conventional one but the area efficiency of NCP-2 is improved as much as 71.8% over the conventional one, when the $V_{PP}/V_{DD}$ ratio is 3.5 and $V_{DD}$=1.8V.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.530-533
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• 1998

In this paper, a new scheme of a boosted voltage generator (BVG) is designed for low powr DRAM's. The designed BVG can supply stable $V_{pp}$ using a new circuit operting method. This method controls charge pumping capability by switching the supply voltage and ring oscillator frequency of driving circuit, so the BVG can save area and reduce the powr dissipation during $V_{pp}$ maintaining period. The charge pumping circuit of the BVG suffers no $V_{T}$ loss and is to be applicable to low-voltage DRAM's. $V_{pp}$ level detecting circuit can detect constant value of $V_{pp}$ against temperature variation. The level of $V_{pp}$ varies -0.55%~0.098% during its maintaining period. Charge pumping circuit can make $V_{pp}$ level up to 2.95V with $V_{cc}$ =1.5V. The degecting level of $V_{pp}$ level detecting circuit changes -0.34% ~ 0.01% as temperature varies from -20 to 80.deg. C. The powr dissipation during V.$_{pp}$ maintaining period is 4.1mW.W.1mW.