• 한국통신학회논문지
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• 제25권6B호
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• pp.114-114
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• 2000

In this paper, a current comparative frequency automatic tuning circuit for the CMOS bandpass filter are designed with the new architecture. And also, when the designed circuit is compared the typical tuning circuit, it has very simple architecture that is composed of the current comparator and charge pump and operated in 2V power supply. The proposed tuning circuit automatically compensate the difference between the operating current of the integrator and the reference current which is specified. Using CMOS 0.25um parameter, a CMOS bandpass active filter with center frequency(f0= 100MHz) is designed, and according to the transister size the variation of the center frequency is simulated. As the HSPIC simulation results, the tuning operating of the proposed current comparative frequency automatic tuning circuit is verified.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.435-436
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• 2008

This paper presents a dual band frequency synthesizer for GSM and Wideband CDMA which is designed in a standard 0.13um CMOS 1P6M process. The shared components include phase frequency detector (PFD), charge pump (CP), loop filter, integer frequency divider(128/129 DMP, 4bit PC, 3bit SC) and Low noise Ring-VCO. A high-speed low power dual modulus prescaler is proposed to operate up to 2.1GHz at 3.3V supply voltage with 2mW power consumption by simulation. The simulated phase noise of VCO is -101dBc/Hz at 200kHz offset frequency from 1.9GHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.459-460
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• 2008

In this paper, a 10Gbps clock and data recovery circuit is designed in $0.18{\mu}m$ CMOS technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a charge pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.2ps and a peak-to-peak recovered data jitter of 8ps while consuming about 80mW from a 1.8V supply.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1189-1192
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• 2003

본 논문에서는 노이즈를 고려한 PLL를 설계하였다. 30Mhz∼300Mhz으로 동작하는 VCO를 설계하였다. VCO를 평균 250Mhz으로 동작하도록 하고 reference 주파수, 62.5Mhz로 locking하는 PLL를 설계를 하였다. 300Mhz PLL의 기본적인 구조로 PLL은 PFD(Phase frequency detector), CP(Charge Pump), LF(Loop filter), VCO(Voltage controlled Oscillator)와 Divider로 구성되었다. PFD과 CP는 Dead Zone를 줄이고, 큰 gm를 가지도록 설계를 하였다. PLL에서 가장 중요한 블락인, VCO는 One Chip으로 설계하기 위해 Ring Oscillator로 설계를 하였다. 2.5V 62.5MHZ의 외부 신호를 300MHZ을 발진하는 VCO에서 분주하여 clock synthesizer를 설계하였다. 본 논문은 Hynix0.25공정을 사용하여 설계를 하였으며, 2.5V의 공급 전원을 사용하였다.

• 대한전자공학회논문지SD
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• 제40권6호
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• pp.442-446
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• 2003

본 논문에서는 몸체효과와 문턱전압 손실이 제거된 새로운 2-단계 2-위상 VPP 전하펌프 발생기를 제안하였다. 새롭게 제안된 회로의 동작을 검증하기 위하여 0.18um Triple-Well CMOS 공정을 사용하였으며, VPP의 전압 레벨은 VDD가 문턱전압 이상일 때 3VDD가 공급되는 결과를 얻었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.241-246
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• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.465-466
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• 2006

In this paper, novel analog duty cycle corrector (DCC) with a digital duty error detector is proposed. The digital duty error detector measures the duty error of the clock and converts it into a digital code. This digital code is then used to accurately correct the duty ratio by adaptively steering the charge-pump current. The proposed duty cycle corrector was implemented using an 80nm DRAM process with 1.8V supply voltage. The simulation result shows that the proposed duty cycle corrector improves the settling time up to $70{\sim}80%$ at 500MHz clock frequency for the same duty correction accuracy as the conventional analog DCC.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.1202-1205
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• 2000

Germicidal lamps efficiently emit a large amount of ultraviolet rays 253.7nm which have excellent germicidal effect. The lamps are primarily useful for sterilization of air, the surface of various materials and water or liquid. In this paper, analysis of the charge pump power factor correction inverter for driving a 65W UV lamp and electrical characteristics of the lamp are discussed. The operation of the inverter circuit. in which the lamp is included as a load, is analyzed. Experimental results of the inverter circuit are also presented.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.197-198
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• 2007

In this paper, a 10Gbps Clock and Data Recovery circuit is designed in $0.18{\mu}m$ CMOS Technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a Charge Pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.1ps and a peak-to-peak recovered data jitter of 8ps while consuming about 44mW from a 1.8V supply.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2017년도 춘계학술대회
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• pp.697-699
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• 2017

본 논문에서는 D 플립플롭과 보조 전하펌프를 사용하여 작은 크기의 위상고정루프를 제안하였다. 단일 커패시터를 사용하여 크기가 작기 때문에 위상고정루프의 집적화가 가능하다. 제안된 위상고정루프는 HSPICE로 시뮬레이션 하였으며, 1.8V $0.18{\mu}m$ CMOS 공정을 사용하였다.