Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 2007.10a
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- Pages.197-198
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- 2007
Design of a 10Gbps CMOS Clock and Data Recovery Circuit
10Gbps CMOS 클록/데이터 복원회로 설계
- Cha, C.H. (Dept. of Electronic Engineering University of Incheon) ;
- Shim, H.C. (Dept. of Electronic Engineering University of Incheon) ;
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Jeon, S.H.
(Dept. of Electronic Engineering University of Incheon) ;
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Yu, C.G.
(Dept. of Electronic Engineering University of Incheon)
- Published : 2007.10.26
Abstract
In this paper, a 10Gbps Clock and Data Recovery circuit is designed in
Keywords