• 한국전자통신학회논문지
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• 제7권4호
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• pp.833-837
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• 2012

SC1(Standard Cleaning) 시간을 줄여 STI 측벽에서의 실리콘 손실 및 과도절개를 최소화하여 DRAM에서의 데이터 유지시간을 증가시키는 방법을 제안한다. SC1 시간 최적화를 통해 STI 상층 모서리부에서의 기생 전기장을 약화시킴으로서 Inverse Narrow Width 효과를 감소시키면 셀 트랜지스터의 Subthreshold 누설의 증가없이 채널 도핑농도가 감소하게 된다. 이것은 셀 접합에서 P-Well간 공핍 영역에서의 전기장을 최소화하여 일드나 데이터 유지시간의 증가를 보여 주었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.497-497
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• 2013

Semiconducting amorphous InGaZnO (a-IGZO) has attracted significant research attention as improved deposition techniques have made it possible to make high-quality a-IGZO thin films. IGZO thin films have several advantages over thin film transistors (TFTs) based on other semiconducting channel layers.The electron mobility in IGZO devices is relatively high, exceeding amorphous Si (a-Si) by a factor of 10 and most organic devices by a factor of $10^2$. Moreover, in contrast to other amorphous semiconductors, highly conducting degenerate states can be obtained with IGZO through doping, yet such a state cannot be produced with a-Si. IGZO thin films are capable of mobilities greaterthan 10 $cm^2$/Vs (higher than a-Si:H), and are transparent at visible wavelengths. For oxide semiconductors, carrier concentrations can be controlled through oxygen vacancy concentration. Hence, adjusting the oxygen partial pressure during deposition and post-deposition processing provides an effective method of controlling oxygen concentration. In this study, we deposited IGZO thinfilms at optimized conditions and then analyzed the film's electrical properties, surface morphology, and crystal structure. Then, we explored how to generate IGZO thin films using DC magnetron sputtering. We also describe the construction and characteristics of a bottom-gate-type TFT, including the output and transfer curves and bias stress instability mechanism.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.82-82
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• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• 대한전자공학회논문지
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• 제26권5호
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• pp.38-45
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• 1989

보론이 100ppm으로 도우핑된 비정질 실리콘을 이용한 쌍극 박막 트랜지스터를 CVD 방법으로 제작하여 전기적 특성을 조사하였다. 쌍극 박막 트랜지스터에 인가한 트레인 전압이 증가하면 정공채널의 드레인 전류는 전자와 정공의 주입에 의해 크게 증가한다. 또한 게이트 전압의 인가 시간에 따른 드레인 전류는 streched exponential로 감소하는데, 이는 전자축적층에 의해 생기는 댕글린 본드 밀도의 변화가 수소의 확산과 동일한 시간 의존성을 갖는 것을 의미한다. 이러한 실험 결과로 부터 보론이 도우핑된 수소화된 비정질 실리콘에 게이트 전압을 인가하거나, 빛 조사시 도우핑 효율이 변화함을 알 수 있다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.751-754
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• 2003

Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with pseudomorphic HEMTs. We have studied the calibration on the DC and RF characteristics of the MHEMT device using I $n_{0.53}$G $a_{0.47}$As/I $n_{0.52}$A1$_{0.48}$As modulation-doped heterostructure on the GaAs wafer. For the optimized device performance simulation, we calibrated the device performance of 0.1-${\mu}{\textrm}{m}$ $\Gamma$-gate MHEMT fabricated in our research center using the 2D ISE-DESSIS device simulator. With this calibrated parameter set, we have obtained very good reproducibility. The device simulation on the DC and RF characteristics exhibits good reproducibility for our 0.1-${\mu}{\textrm}{m}$ -gate MHEMT device compared with the measurements. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.ormance.

• 한국전기전자재료학회논문지
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• 제20권5호
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• pp.394-398
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• 2007

A simple doping method to fabricate a very thin channel body of the nano-scaled n-type fin field-effect-transistor (FinFET) by arsenic solid-Phase-diffusion (SPD) process is presented. Using the As-doped spin-on-glass films and the rapid thermal annealing for shallow junction, the n-type source-drain extensions with a three-dimensional structure of the FinFET devices were doped. The junction properties of arsenic doped regions were investigated by using the $n^+$-p junction diodes which showed excellent electrical characteristics. The n-type FinFET devices with a gate length of 20-100 nm were fabricated by As-SPD and revealed superior device scalability.

• Bulletin of the Korean Chemical Society
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• 제24권3호
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• pp.285-290
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• 2003

An analytical method for the simultaneous determination of trace Ge, As and Se in biological samples by inductively coupled plasma/mass spectrometry has been investigated. The effects of added organic gas into the coolant argon gas on the analyte signal were studied to improve the detection limit, accuracy and precision. The addition of a small amount of methane (10 mL/min.) into the coolant gas channel improved the ionization of Ge, As and Se. The analytical sensitivity of the proposed Ar/CH₄system was superior by at least two-fold to that of the conventional Ar method. In the present method, the detection limits obtained for Ge, As and Se were 0.014, 0.012 and 0.064 ㎍/L, respectively. The analytical reliability of the proposed method was evaluated by analyzing the certified standard reference materials (SRM). Recoveries of 99.9% for Ge, 103% for As, 96.5% for Se were obtained for NIST SRM of freeze dried urine sample. The proposed method was also applied to the biological samples.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.199-199
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• 2008

이 실험은 NVM의 Oxide, Nitride, Oxide nitride층별 blocking, trapping and tunneling 속성에 대해서 밝히고자 한다. gate 전극은 값싸고 전도도가 좋은 알루미늄을 사용한다. 유리기판위에 Silicon nitride층을 20nm로 코팅하고 Silicon dioxide층을 10nm로 코팅한다. 그리고 amorphous Silicon material이 증착된다. Poly Silicon은 Solid Phase Crystallization 방법을 사용하였다. 마지막 공정으로 p-doping은 ion shower에 의한 방법으로 drain과 source 전극을 생성하였다. gate가 biasing 될 때, p-channel은 source와 drain 사이에서 형성된다. Oxide Nitride Oxide nitride (ONO) 층은 각각 12.5nm/20nm/2.3nm의 두께로 만들었다. 전하는 Program process 중에 poly Silicon층에서 Silicon Oxide nitride tunneling층을 통하여 움직이게 된다. 그리고 전하들은 Silicon Nitride층에 머무르게 된다. 그 전하들은 erasing process 중에 trapping 층에서 poly Silicon 층으로 되돌아 간다. Silicon Oxide blocking층은 trapping층으로 전하가 나가는 것을 피하기 위하여 더해진다. 이 논문에서 Programming process와 erasing process의 Id-Vg 특성곡선을 설명한다. Programming process에 positive voltage를 또는 erasing process에 negative voltage를 적용할 때, Id-Vg 특성 곡선은 왼쪽 또는 오른쪽으로 이동한다. 이 실험이 보여준 결과값에 의해서 10년 이상의 저장능력이 있는 메모리를 만들 수 있다. 그러므로, NVM의 중요한 두 가지 성질은 유지성과 내구성이다.

• 반도체디스플레이기술학회지
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• 제10권1호
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• pp.63-73
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• 2011

Metamorphic HEMTs (MHEMTs) have emerged as excellent challenges for the design and fabrication of high-speed HEMTs for millimeter-wave applications. Some of improvements result from improved mobility and larger conduction band discontinuity in the channel, leading to more efficient modulation doping, better confinement, and better device performance compared with conventional pseudomorphic HEMTs (PHEMTs). For the optimized device design and development, we have performed the calibration on the DC characteristics of our fabricated 0.1 ${\mu}m$ ${\Gamma}$-gate MHEMT device having the modulation-doped $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}$As heterostructure on the GaAs wafer using the hydrodynamic transport model of a commercial 2D ISE-DESSIS device simulator. The well-calibrated device simulation shows very good agreement with the DC characteristic of the 0.1 ${\mu}m$ ${\Gamma}$-gate MHEMT device. We expect that our calibration result can help design over-100-GHz MHEMT devices for better device performance.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.369-372
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• 2004

The characteristics of antimony implants are relatively well-known. Antimony has lower diffusion coefficient, shorter implantation range, and smaller scattering as compared with conventional dopants such as phosphorous and arsenic. It has been commonly used in the doping of buried layer in Bi-CMOS process. In this paper, characteristics and appropriate condition of monitoring in antimony implant beam tuning using $Sb_2O_3$ were investigated to get a reliable process. TW(Thema Wave) and Rs(Sheet Resistance) test were carried out to set up condition of monitoring for stable operation through the periodic inspection of instruction condition. The monitoring was progressed at the point that the slant of Rs varied significantly to investigate the variation of instruction accurately.