• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.23-30
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• 2006

This paper describes the short-channel effect(SCE), corner effect of nano-scale MuGFETs(Multiple-Gate FETs) by three-dimensional simulation. We can extract the equivalent gate number of MuGFETs(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4) by threshold voltage model. Using the extracted gate number(n) we can calculate the natural length for each gate devices. We established a scaling theory for MuGFETs, which gives a optimization to avoid short channel effects for the device structure(silicon thickness, gate oxide thickness). It is observed that the comer effects decrease with the reduction of doping concentration and gate oxide thickness when the radius of curvature is larger than 17 % of the channel width.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.2
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• Journal of information and communication convergence engineering
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• v.16 no.1
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• pp.43-47
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• 2018

The existing modeling of avalanche dominated breakdown in double gate MOSFETs (DGMOSFETs) is not relevant for 10 nm gate lengths, because the avalanche mechanism does not occur when the channel length approaches the carrier scattering length. This paper focuses on the punch through mechanism to analyze the breakdown characteristics in 10 nm DGMOSFETs. The analysis is based on an analytical model for the thermionic-emission and tunneling currents, which is based on two-dimensional distributions of the electric potential, obtained from the Poisson equation, and the Wentzel-Kramers-Brillouin (WKB) approximation for the tunneling probability. The analysis shows that corresponding flat-band-voltage for fixed threshold voltage has a significant impact on the breakdown voltage. To investigate ambiguousness of number of dopants in channel, we compared breakdown voltages of high doping and undoped DGMOSFET and show undoped DGMOSFET is more realistic due to simple flat-band-voltage shift. Given that the flat-band-voltage is a process dependent parameter, the new model can be used to quantify the impact of process-parameter fluctuations on the breakdown voltage.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.342-343
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• 2012

We studied the Drain-Induced-Barrier-Lowering (DIBL) effect by different drain engineering. One other drain engineering is symmetric source-drain n-channel MOSFETs (SSD NMOSs), the other drain engineering is asymmetric source-drain n-channel MOSFETs (ASD NMOSs). Devices were fabricated using state of art 40 nm dynamic-random-access-memory (DRAM) technology. These devices have different modes which are deep drain junction mode in SSD NMOSs and shallow drain junction mode in ASD NMOSs. The shallow drain junction mode means that drain is only Lightly-Doped-Drain (LDD). The deep drain junction mode means that drain have same process with source. The threshold voltage gap between low drain voltage ($V_D$=0.05V) and high drain voltage ($V_D$=3V) is 0.088V in shallow drain junction mode and 0.615V in deep drain junction mode at $0.16{\mu}m$ of gate length. The DIBL coefficients are 26.5 mV/V in shallow drain junction mode and 205.7 mV/V in deep drain junction mode. These experimental results present that DIBL effect is higher in deep drain junction mode than shallow drain junction mode. These results are caused that ASD NMOSs have low drain doping level and low lateral electric field.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.382-384
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• 2009

In this study, high stable oxide thin-film transistors (TFTs) have been developed by using several approaching techniques, which including a change of the channel composition ratio in multi-component oxide semiconductors, a change of TFT structure with interfacial dielectric layers, a control of interface roughness, a channel-doping method, and so on.

• Journal of IKEEE
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• v.14 no.4
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• pp.277-282
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• 2010

In this paper, we proposed ZnO trench Static Induction Transistor(SIT). Because The compound semiconductor had superior thermal characteristics, ZnO and SiC power devices is next generation power semiconductor devices. We carried out modeling of ZnO SIT with 2-D device and process simulator. As a result of modeling, we obtained 340V breakdown voltage. The channel thickness was 3um and the channel doping concentration is 1e17cm-3. And we carried out thermal characteristics, too.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.8
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• pp.674-677
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• 2011

The dependency of sputtering power on the electrical performances in amorphous HIZO-TFT (hafnium-indium-zinc-oxide thin film transistors) has been investigated. The HIZO channel layers were prepared by using radio frequency (RF) magnetron sputtering method with different sputtering power at room temperature. TOF-SIMS (time of flight secondary ion mass spectrometry) was performed to confirm doping of hafnium atom in IZO film. The field effect mobility (${\mu}FE$) increased and threshold voltage ($V_{th}$) shifted to negative direction with increasing sputtering power. This result can be attributed to the high energy particles knocking-out oxygen atoms. As a result, oxygen vacancies generated in HIZO channel layer with increasing sputtering power resulted in negative shift in Vth and increase in on-current.

• Transactions on Electrical and Electronic Materials
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• v.13 no.2
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• pp.69-72
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• 2012

In this study, deposition of low-dielectric constant SiOC(H) films by conventional plasma-enhanced chemical vapor deposition (PECVD) were investigated through various characterization techniques. The results show that, with an increase in the plasma power density, the relative dielectric constant (k) of the deposited films decreases whereas the refractive index increases. This is mainly due to the incorporation of organic molecules with $CH_3$ group into the Si-O-Si cage structure. It is as confirmed by FT-IR measurements in which the absorption peak at 1,129 $cm^{-1}$ corresponding to Si-O-Si cage structure increases with power plasma density. Electrical characterization reveals that even after fast thermal annealing process, the leakage current density of the deposited films is in the order of $10^{-11}$ A/cm at 1.5 MV/cm. The reliability of the SiOC(H) film is also further characterized by using BTS test.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.166-170
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• 1991

An advanced on-resistance model of VDMOS devices in the low voltage regime is proposed and verified by 2-D device simulations. The model considers the lateral gaussian doping profiles in the channel region and exact current spreading angles in the epitaxial layer for both linear and cellular geometries by employing the conformal mapping. It is found out that the on-resistance of low voltage VDMOS may be overestimated considerably if it is analyzed by the conventional method. The 2-D device simulation results show that the proposed model is valid for all ranges of cell spacings and breakdown voltages.

• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.87-90
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• 2014

The effects of electric field frequency on the ac electrical treeing phenomena in an epoxy/reactive diluent/layered silicate (1.5 wt%) were carried out, in needle-plate electrode arrangement. A layered silicate was exfoliated in an epoxy base resin, by using our ac electric field apparatus. To measure the treeing propagation rate, constant alternating current (AC) of 10 kV with three different electric field frequencies (60, 500 and 1,000 Hz) was applied to the specimen, in needle-plate electrode arrangement, at $30^{\circ}C$ of insulating oil bath. As the electric field frequency increased, the treeing propagation rate increased. At 500 Hz, the treeing propagation rate of the epoxy/PG/nanosilicate system was $0.41{\times}10^{-3}$ mm/min, which was 3.4 times slower than that of the epoxy/PG system. The electrical treeing morphology was dense bush type at 60 Hz; however, as the frequency increased, the bush type was changed to branch type, having few branches, with very slow propagation rate.