• Proceedings of the Korean Society of Sericultural Science Conference
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• 2003.10a
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• pp.100-101
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• 2003

Gap junctions are membrane channels that directly connect the cytoplasm of neighboring cells, allowing the exchange of ions and small molecules. Two analogous families of proteins, the connexins and innexins are the channel-forming molecular vertebrates and invertebrates, respectively. Here, we present the molecular cloning and sequences analysis of novel innexiins, Binx2, expressed during Bombyx mori embryonic development. (omitted)

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.351-354
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• 1998

In this paper, electrical characteristics of an n-channel Si MOSFET with L$_{s}$=0.6.mu.m under optical illumination are charaterized on wafer. Energetic photons with .gamma.=830nm, hv=1.494eV, P$_{opt}$=300mW are injected near the drain junction, the most photoresponsive region in the device, via optical fiber. We observed significantly increased drain current and transconductance, which is considered to be useful for the implementation of OEICs on silicon substrate, under optical control with P$_{opt}$=300mW. Optical power-dependent physical mechanisms responsible for the variation of electrical characteristics under optical input are also reported.d.d.d.

• Journal of the Korean Society of Visualization
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• v.8 no.4
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• pp.43-47
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• 2010

We demonstrate the droplet bistability in a microchannel which has two symmetric necks that operate as capillary valves. It is shown that there are certain flow conditions, determined by droplet velocity and droplet size, to achieve bistability. Droplet bistabililty allows simple but precise control of droplet at a bifurcation channel. Therefore, by an appropriate channel design to induce droplet bistability, we can distribute droplets at a junction passively in the manner of perfect alternation and perfect switching in the choice of the outlets.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.4
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• pp.112-120
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• 1996

With the MOsES (mask oxide sidewall etch scheme)process which uses the conventional i-line stepper and isotropic wet etching, CMOSFET's with fine gate pattern of 0.1.mu.m CMOSFET device, the screening oxide is deposited before the low energy ion implantation for source/drain extensions and two step sidewall scheme is adopted. Through the characterization of 0.1.mu.m CMOSFET device, it is found that the screening oxide deposition sheme has larger capability of suppressing the short channel effects than two step sidewall schem. In cse of 200.angs.-thick screening oxide deposition, both NMOSFET and PMOSFET maintain good subthreshold characteristics down to 0.1.mu.m effective channel lengths, and show affordable drain saturation current reduction and low impact ionization rates.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.9
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• pp.771-774
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• 2003

In this paper, the programming characteristics of the multi-bit devices based on SONOS structure are investigated. Our devices have been fabricated by 0.35 $\mu\textrm{m}$ complementary metal-oxide-semiconductor (CMOS) process with LOCOS isolation. In order to achieve the multi-bit operation per cell, charges must be locally frapped in the nitride layer above the channel near the source-drain junction. Programming method is selected by Channel Hot Electron (CUE) injection which is available for localized trap in nitride film. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve are investigated. The multi-bit operation which stores two-bit per cell is investigated. Also, Hot Hole(HH) injection for fast erasing is used. The fabricated SONOS devices have ultra-thinner gate dielectrics and then have lower programming voltage, simpler process and better scalability compared to any other multi-bit storage Flash memory. Our programming characteristics are shown to be the most promising for the multi-bit flash memory.

• The Korean Journal of Physiology and Pharmacology
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• v.19 no.1
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• pp.73-79
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• 2015

Connexins (Cx) are membrane proteins and monomers for forming gap junction (GJ) channels. Cx46 and Cx50 are also known to function as conductive hemichannels. As part of an ongoing effort to find GJ-specific blocker(s), endocrine disruptors were used to examine their effect on Cx46 hemichannels expressed in Xenopus oocytes. Voltage-dependent gating of Cx46 hemichannels was characterized by slowly activating outward currents and relatively fast inward tail currents. Bisphenol A (BPA, 10 nM) reduced outward currents of Cx46 hemichannels up to ~18% of control, and its effect was reversible (n=5). 4-tert-Octylphenol (OP, $1{\mu}M$) reversibly reduced outward hemichannel currents up to ~28% (n=4). However, overall shapes of Cx46 hemichannel current traces (outward and inward currents) were not changed by these drugs. These results suggest that BPA and OP are likely to occupy the pore of Cx46 hemichannels and thus obstruct the ionic fluxes. This finding provides that BPA and OP are potential candidates for GJ channel blockers.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.51 no.3
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• pp.134-140
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• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.69-75
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• 2003

Cell transistor and data retention time characteristics were studied in 90 nm design rule 512M-bit DRAM, for the first time. And, the characteristics of cell transistor are investigated for different STI gap-fill materials. HDP oxide with high compressive stress increases the threshold voltage of cell transistor, whereas the P-SOG oxide with small stress decreases the threshold voltage of cell transistor. Stress between silicon and gap-fill oxide material is found to be the major cause of the shift of the cell transistor threshold voltage. If high stress material is used for STI gap fill, channel-doping concentration can be reduced, so that cell junction leakage current is decreased and data retention time is increased.

• Journal of IKEEE
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• v.3 no.1 s.4
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• pp.118-125
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• 1999

A capacitance method to extract the metallurgical channel length of LDD MOSFET's, which is defined by the length between the metallurgical junction of substrate and source/drain under the gate, is presented. The gate capacitances of the finger type and plate type LDD MOSFET gate test patterns with same total gate area are measured. The gate bias of each pattern is changed, and the capacitances are measured with source, drain, and substrate bias grounded. The differences between two test pattern's capacitance data are plotted. The metallurgical channel length is extracted from the peak data at a maximum point using a simple formula. The numerical simulation using two-dimensional device simulator is performed to verify the proposed method.