• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.15-22
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• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.64-71
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• 2020

eFuse OTP memory IP is required to trim the analog circuit of the gate driving chip of the power semiconductor device. Conventional NMOS diode-type eFuse OTP memory cells have a small cell size, but require one more deep N-well (DNW) mask. In this paper, we propose a small PMOS-diode type eFuse OTP memory cell without the need for additional processing in the CMOS process. The proposed PMOS-diode type eFuse OTP memory cell is composed of a PMOS transistor formed in the N-WELL and an eFuse link, which is a memory element and uses a pn junction diode parasitic in the PMOS transistor. A core driving circuit for driving the array of PMOS diode-type eFuse memory cells is proposed, and the SPICE simulation results show that the proposed core circuit can be used to sense post-program resistance of 61㏀. The layout sizes of PMOS-diode type eFuse OTP memory cell and 512b eFuse OTP memory IP designed using 0.13㎛ BCD process are 3.475㎛ × 4.21㎛ (= 14.62975㎛2) and 119.315㎛ × 341.95㎛ (= 0.0408mm2), respectively. After testing at the wafer level, it was confirmed that it was normally programmed.

• Journal of the Korea Society of Computer and Information
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• v.14 no.2
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• pp.157-168
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• 2009

In this paper, a photovoltaic system is designed with a step up chopper and single phase PWM(Pulse Width Modulation) voltage source inverter. Where proposed Synchronous signal and control signal was processed by one-chip microprocessor for stable modulation. The step up chopper operates in continuous mode by adjusting the duty ratio so that the photovoltaic system tracks the maximum power point of solar cell without any influence on the variation of insolation and temperature because solar cell has typical voltage and current dropping character. The single phase PWM voltage source the inverter using inverter consists of complex type of electric power converter to compensate for the defect, that is, solar cell cannot be developed continuously by connecting with the source of electric power for ordinary use. It can cause the effect of saving electric power. from 10 to 20[%]. The single phase PWM voltage source inverter operates in situation that its output voltage is in same phase with the utility voltage. In order to enhance the efficiency of photovoltaic cells, photovoltaic positioning system using sensor and microprocessor was design so that the fixed type of photovoltaic cells and photovoltaic positioning system were compared. In result, photovoltaic positioning system can improved 5% than fixed type of photovoltaic cells. In addition, I connected extra power to the system through operating the system voltage and inverter power in a synchronized way by extracting the system voltage so that the phase of the system and the phase of single-phase inverter of PWM voltage type can be synchronized. And, It controlled in order to provide stable pier to the load and the system through maintaining high lurer factor and low output power of harmonics.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.10
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• pp.1-9
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• 2001

The MAC (Medium Access Control) protocol is needed for the OLT(Optical Line Termination) to allocate bandwidth to ONUs(Optical Network Units) and ONTs(Optical Network Terminations) dynamically in the ATM PON(Passive Optical Network). With the protocol, the OLT gathers ONUs' informations and provides grants efficiently to each ONU. Two important functions of the MAC protocol is the grant request procedure and the grant distribution algrithm. The latter has the greatest arithmetic portion in the TC(Transmission Convergence) module, occupies a relatively large portion of the overall chip area, has often been the limiting factor in terms of speed, and should be designed to guarantee the quality of service for various traffics. In this paper, we implement the MAC with the FPGA which can allocate grants dynamically according to the queue length information and the number of active ONUs and distribute grants uniformly to minimize the cell delay variation for each ONU. The structure of the MAC scheduler for the dynamic bandwidth assignment has a programmable look-up table. Also, it has a simple structure, the less chip area, and the lower delay time.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.36 no.5
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• pp.475-479
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• 2012

We present a novel polymer fabrication process involving direct UV patterning of a hyperbranched polymer, AEO3000. Compared to PDMS, which is the most widely used polymer in bioMEMS devices, the present polymer has advantages with regard to electrode integration and fast fabrication. We designed a four-chip microelectrofluidic bench having three electrical pads and two fluidic I/O ports. We integrated a microfluidic mixer and a cell separator on the bench to characterize the interconnection performance and sample manipulation. Electrical and fluidic characterization of the microfluidic bench was performed. The measured electrical contact resistance was $0.75{\pm}0.44{\Omega}$, which is small enough for electrical applications, and the pressure drop was 8.3 kPa, which was 39.3% of the value in the tubing method. By performing yeast mixing and a separation test in the integrated module on the bench, we successfully showed that the interconnected chips could be used for bio-sample manipulation.

• Journal of Sensor Science and Technology
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• v.7 no.4
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• pp.263-270
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• 1998

Surface Plasmon Resonance (SPR) sensor system, has rapid response and high sensitivity, can be applicable for detecting reaction times of many biospecific interactions. A SPR sensor system was constructed to detect the antigen-antibody reactions of salmonella and hIgG (human immunoglobulin G). Sensor chips made of gold thin film were used for detecting biological bindings of antigen and antibody reactions. The antigen and antibody reactions for salmonella and hIgG were carried out with various time intervals to observed characteristics of these reactions using SPR sensor system. The resonance angle shift changes were clearly observed at the time of salmonella or hIgG antibody injection into sample cell since each antibody was self-assembled on gold chip surface of the sensor. It was found that the antibodies of salmonella and hIgG reacted with its sensor chip surface in 10 minutes and 60 minutes respectively. And the antigens of both salmonella and hIgG were bound to its antibody within 1 minute.

• Journal of Life Science
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• v.26 no.7
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• pp.789-795
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• 2016

A lymph node (LN) is one of the secondary lymphoid organs. An LN consists of a complicated 3 dimensional frame structure and several stromal cells. Fibroblastic reticular cells (FRC) are distributed in the T zone for interaction with T cells. FRC secrete homing chemokines such as CCL19 and CCL21. Moreover, FRC play a pivotal role in the production of extracellular matrix (ECM) into LN for ECM reorganization against pathogen infections. However, not much is known about the involvement of the immune reaction of FRC. The present report is for the characterization of FRC on immune response. For this, FRC were positioned in several infected situations such as co-culture with macrophage, lipopolysaccharide (LPS), and TNFα stimulation. When a co-culture between FRC and macrophage was performed, a morphological change in FRC was observed, and empty space between FRCs was created by this change. The soluble ICAM-1 protein level was up-regulated by co-culturing with Raw264.7 and the treatment of the ROCK inhibitor Y27632. The activity of matrix metalloproteinase (MMP) was up-regulated by LPS onto FRC. Furthermore, the inflammatory cytokine TNFα regulated the expression of ECM in FRC by a gene chip assay. Collectively, it suggests that FRC are involved in immune reactions.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.4
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• pp.913-920
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• 2011

In this paper, a logic process based 1-kbit EEPROM IP for RFID tag chips of 900MHz is designed. The cell array of the designed 1-kbit EEPROM IP is arranged in a form of four blocks of 16 rows x 16 columns, that is in a two-dimensional arrangement of one-word EEPROM phantom cells. We can reduce the IP size by making four memory blocks share CG (control gate) and TG (tunnel gate) driver circuits. We propose a TG switch circuit to supply respective TG bias voltages according to operational modes and to keep voltages between devices within 5.5V in terms of reliability in order to share the TG driver circuit. Also, we can reduce the power consumption in the read mode by using a partial activation method to activate just one of four memory blocks. Furthermore, we can reduce the access time by making BL (bit line) switching times faster in the read mode from reduced number of cells connected to each column. We design and compare two 1-kbit EEPROM IPs, two blocks of 32 rows ${\times}$ 16 columns and four blocks of 16 rows ${\times}$ 16 columns, which use Tower's $0.18{\mu}m$ CMOS process. The four-block IP is smaller by 11.9% in the layout size and by 51% in the power consumption in the read mode than the two-block counterpart.

• Proceedings of the Korean Society for Bioinformatics Conference
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• 2003.10a
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• pp.66-72
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• 2003

Toxicogenomics is now emerging as one of the most important genomics application because the toxicity test based on gene expression profiles is expected more precise and efficient than current histopathological approach in pre-clinical phase. One of the challenging points in Toxicogenomics is the construction of intelligent database management system which can deal with very heterogeneous and complex data from many different experimental and information sources. Here we present a new Toxicogenomics database developed as a part of 'Toxicogenomics for Efficient Safety Test (TEST) project'. The TEST database is especially focused on the connectivity of heterogeneous data and intelligent query system which enables users to get inspiration from the complex data sets. The database deals with four kinds of information; compound information, histopathological information, gene expression information, and annotation information. Currently, TEST database has Toxicogenomics information fer 12 molecules with 4 efficacy classes; anti cancer, antibiotic, hypotension, and gastric ulcer. Users can easily access all kinds of detailed information about there compounds and simultaneously, users can also check the confidence of retrieved information by browsing the quality of experimental data and toxicity grade of gene generated from our toxicology annotation system. Intelligent query system is designed for multiple comparisons of experimental data because the comparison of experimental data according to histopathological toxicity, compounds, efficacy, and individual variation is crucial to find common genetic characteristics .Our presented system can be a good information source for the study of toxicology mechanism in the genome-wide level and also can be utilized fur the design of toxicity test chip.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.15-21
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• 2011

In this paper, an energy management circuit for solar energy harvesting system is designed in $0.35{\mu}m$ CMOS technology. The solar energy management system consists of an ISC(Integrated Solar Cell), a voltage booster, and an MPPT(Maximum Power Point Tracker) control unit. The ISC generates an open circuit voltage of 0.5V and a short circuit current of $15{\mu}A$. The voltage booster provides the following circuit with a supply voltage about 1.5V. The MPPT control unit turns on the pMOS switch to provide the load with power while the ISC operates at MPP. The SEMU(Solar Energy Management Unit) area is $360{\mu}m{\times}490{\mu}m$ including pads. The ISC area is $500{\mu}m{\times}2000{\mu}m$. Experimental results show that the designed SEMU performs proper MPPT control for solar energy harvested from the ISC. The measured MPP voltage range is about 370mV∼420mV.