• Journal of Power Electronics
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• v.7 no.4
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• pp.310-317
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• 2007

In this paper, an analysis and hysteretic controller design of a $3^{rd}$ order buck converter is presented. The proposed hysteretic controller consists of an inner current-loop, just like the conventional cascade control scheme, and an outer voltage-loop for load voltage regulation. Although it is possible to include an inner current loop from different branches of the converter, from the feasibility and operational point of view, the load side capacitor current would be the better choice. The addition of an inner current-loop improves the dynamic performance of the converter while preserving the robustness of the hysteretic control. The controller formulation and closed-loop converter performance analysis are validated through computer simulations. Few experimental results of the proposed converter are given and compared with the buck converter.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.1035-1037
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• 1992

Generally, fuel cell has characteristics of low voltage, large current and voltage variation under load change. Therefore, DC output voltage of fuel cell is too low to convert into AC with high efficiency and good performance. For this reason, fuel cell generating system is composed of DC-DC converter and inverter in cascade. This paper used 2-phase boost DC-DC converter to obtain low distortion waveform and reduce input-output current ripple, and discussed inverter which can be operated in independent drive mode and utility line interface drive mode. Then, the change of modes can be achived smoothly.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1637-1640
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• 2005

This paper presents a technique for electromagnetic field analysis on surge response due to Mid-span back-flashovers effects in lightning protection system of 500 kV EHV single circuit transmission tower by the neural networks method. These analyses are based on modeling lightning return stroke as well as on coupling the electromagnetic fields of the stroke channel to the line. The ground conductivity influences both the electric field as well as the coupling mechanism and hence the magnitude and wave shape of the induced voltage. The technique can be used to analyzed the corona voltage effect, the effective of stroke to the span tower, the surge impedance of transmission lines. The maximum voltage from flashovers effects in the lines. The model is compatible with general electromagnetic transients programs such as the ATP-EMTP. The simulation results show that this study analyses for time-domain with those produced by a cascade multi-section model, the surge impedance of a full-sized tower hit directly by a lightning stroke is discussed.

• Journal of Power Electronics
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• v.5 no.1
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• pp.76-82
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• 2005

A novel variant of full multi-modulation applications to diode-clamped and cascade multilevel inverter-termed single carrier multi-modulation is presented. The proposed PWM-technique is advantageous for its simple implementation. The correlation between multi-carrier and single-carrier multi-modulations is deduced. For the PWM methods, a mathematical model of voltage source inverter and general algorithm for the multi-modulating modulator are proposed. The theory is demonstrated by simulation results

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.1-2
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• 2017

본 논문은 영전압 스위칭을 갖는 고승압 캐스케이드 동기정류 부스트 컨버터를 제안한다. 제안된 컨버터는 캐스케이드 부스트 컨버터 기반으로 고승압을 달성하기 위해 결합 인덕터를 적용하였으며 컨버터의 효율 향상을 위해 추가 회로와 동기정류방식을 적용하여 기존 출력 다이오드의 도통 손실이 감소하였으며 영전압 스위칭을 달성하였다. 제안된 컨버터는 이론적 해석과 200[W]급 하드웨어 시작품을 제작하여 검증하였다.

• ETRI Journal
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• v.32 no.3
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• pp.457-459
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• 2010

A low-power down-sampling mixer in a low-power digital 65 nm CMOS technology is presented. The mixer consumes only 830 ${\mu}W$ at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 ${\pm}$1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of -5.9 dBm is achieved.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2139-2149
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• 2016

In this study, a new type of cascaded modular multilevel inverters (CMMLIs) is presented which is able to produce a considerable number of output voltage levels with a reasonable number of components. Accordingly, each series stage of the proposed CMMLI is comprised of two same basic units that are connected with each other through two unidirectional power switches without aiming any of the full H-bridge cells. In addition, since the potentiality for generating a higher number of output voltage levels in CMMLIs hinges on the magnitude of the dc voltage sources used in each series unit, in the rest of this paper, four different algorithms for determining an appropriate value for the dc sources' magnitude are also presented. In the following, a comprehensive topological analysis between some CMMLI structures reported in the literature and proposed structure along with several simulation and experimental results will be also given to validate the lucrative benefits and viability of the proposed topology.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.5
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• pp.401-406
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• 2005

Two dimensional MEDICI simulator is used to study the electrical characteristics of Dual Gate Emitter Switched Thyristor. The simulation is done in terms of the current-voltage characteristics with the variations of p-base impurity concentrations and current flow. Compared with the other power devices such as MOS Controlled Cascade Thyristor(MCCT), Conventional Emitter Switched Thyristor(C-EST) and Dual Channel Emitter Switched Thyristor(DC-EST), Dual Gate Emitter Switched Thyristor(DG-EST) shows to have tile better electrical characteristics, which is the high latch-up current density and low forward voltage-drop. The proposed DG-EST which has a non-planer u-base structure under the floating N+ emitter indicates to have the better characteristics of latch-up current and breakover voltage in spite of the same turn-off characteristics.

• Journal of Power Electronics
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• v.19 no.1
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• pp.89-98
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• 2019

This paper analyzes the input side performance of a conventional three-phase to single-phase matrix converter (3-1MC). It also presents the input-side waveform quality under this topology. The suppression of low-frequency input current harmonics is studied using the 3-1MC plus capacitance compensation unit. The constraint between the modulation function of the output and compensation sides is analyzed, and the relations among the voltage utilization ratio and the output compensation capacitance, filter capacitors and other system parameters are deduced. For a 3-1MC without large-capacity energy storage, the system performance is susceptible to input voltage imbalance. This paper decouples the inner current of the 3-1MC using a Lyapunov function in the input positive and negative sequence bi-coordinate axes. Meanwhile, the outer loop adopts a voltage-weighted synthesis of the output and compensation sides as a cascade of control objects. Experiments show that this strategy suppresses the low-frequency input current harmonics caused by input voltage imbalance, and ensures that the system maintains good static and dynamic performances under input-unbalanced conditions. At the same time, the parameter selection and debugging methods are simple.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.576-580
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• 2001

This paper presents a casca multilevel PWM rectifier without the isolation transformers for energy build-up at each inverter modules; The features and advantages of the proposed PWM rectifier can be summarized as follows; 1) It realizes the high power high voltage AC/DC power conversion, 2) It uses no transformer which is bulky and heavy, 3) It has hybrid structure so that switching devices can be effectively utilized, 4) It produces high quality AC current even in high power high voltage applications, 5) The input power factor remains unity by simple modulation index control. The multilevel rectifier is analyzed by using the circuit DQ transformation whereby the characteristics and control equations are obtained. Finally, it will be shown that the system simulation reveals the validity of analyses