• 제목/요약/키워드: Capacitance reduction

검색결과 165건 처리시간 0.025초

Fabrication of Graphene Supercapacitors for Flexible Energy Storage

  • Habashi, M. Namdar;Asl, Shahab Khameneh
    • 한국재료학회지
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    • 제27권5호
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    • pp.248-254
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    • 2017
  • In the present work, graphene powder was synthesized by laser scribing method. The resultant flexible light-scribed graphene is very appropriate for use in micro-supercapacitors. The effect of the laser scribing process in reducing graphene oxide (GO) was investigated. GO was synthesized using a chemical mixture of GO solution; then, it was coated onto a LightScribe DVD disk and laser scribed to reduce GO and create laser-scribed graphene (LSG). The CV curves of pristine rGO at various scan rates showed that the ultimate product possesses the ability to store energy at the supercapacitor level. Charge-discharge curves of pristine rGO at two different current densities indicated that the specific capacitance ($C_m$) increases due to the reduction of the discharge current density. Finally, the long-term charge-discharge stability of the LSG was plotted and indicates that the specific capacitance decreases very slightly from its primary capacitance of ${\sim}10F\;cm^{-3}$ and that the cyclic stability is favorable over 1000 cycles.

3차 고조파 주입과 PR 제어기를 이용한 단상 PWM 컨버터의 커패시터 용량 저감 기법 (Capacitance reduction method for single-phase PWM converters using the 3rd harmonic injection and PR controller.)

  • 김규동;양현석;이동명
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2013년도 전력전자학술대회 논문집
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    • pp.1-2
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    • 2013
  • In this paper, we inject input currents having $3^{rd}$ harmonic to reduce the capacitance of DC link capacitors in single-phase converters. If the input current with third harmonic is injected, the required capacitance can be reduced by minimizing the difference between the input and output power. To control the input current, instead of PI control done in rotating frame, PR controller is used with the proposed separate current control method for fundamental and $3^{rd}$ harmonic components. The validity of the proposed method has been demonstrated by simulation results.

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Transistor Sizing Considering Slew Information to Reduce Glitch Power in CMOS Digital Circuit Design

  • Lee, Hyungwoo;Kim, Juho
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -2
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    • pp.1058-1061
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    • 2002
  • This paper presents the method of low power optimization considering the glitch reduction in CMOS circuits. Our algorithm utilizes the information of MOS size, the load capacitance of fan-out, and input slew to calculate the output waveform by using the linear signal model. Therefore, the accurate waveform of glitch can be obtained for estimation of power dissipation caused by glitches. Our algorithm is applied to ISCAS’85 benchmark circuits and experimental results show 23% glitch reduction and 11% total power reduction.

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두 개의 이득 값을 가지는 전압제어발진기를 이용하여 유효 커패시턴스를 크게 하는 위상고정루프 (An Available Capacitance Increasing PLL with Two Voltage Controlled Oscillator Gains)

  • 장희승;최영식
    • 전자공학회논문지
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    • 제51권7호
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    • pp.82-88
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    • 2014
  • 본 논문에서는 두 개의 이득 값을 가지는 전압제어발진기를 이용하여 루프필터 커패시턴스 유효 용량을 배가 시켜 칩 크기를 줄일 수 있는 위상고정루프를 제안하였다. 제안된 위상고정루프에서는 양/음의 두 개의 이득 값을 가지는 전압제어발진기로 루프 필터의 커패시턴스 유효 용량을 배가 시켜 루프필터 커패시터 크기를 1/10로 줄였다. 제안된 위상고정루프는 1.8V $0.18{\mu}m$ CMOS 공정을 이용하여 설계되었다. 시뮬레이션 결과는 기존 구조와 같은 잡음 특성과 위상고정 시간을 보여주었다.

Capacitance-voltage Characteristics of MOS Capacitors with Ge Nanocrystals Embedded in HfO2 Gate Material

  • Park, Byoung-Jun;Lee, Hye-Ryeong;Cho, Kyoung-Ah;Kim, Sang-Sig
    • 한국전기전자재료학회논문지
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    • 제21권8호
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    • pp.699-705
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    • 2008
  • Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

Development of a variable resistance-capacitance model with time delay for urea-SCR system

  • Feng, Tan;Lu, Lin
    • Environmental Engineering Research
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    • 제20권2호
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    • pp.155-161
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    • 2015
  • Experimental research shows that the nitric oxides ($NO_X$) concentration track at the outlet of selective catalytic reduction (SCR) catalyst with a transient variation of Adblue dosage has a time delay and it features a characteristic of resistance-capacitance (RC). The phenomenon brings obstacles to get the simultaneously $NO_X$ expected to be reduced and equi-molar ammonia available to SCR reaction, which finally inhibits $NO_X$ conversion efficiency. Generally, engine loads change frequently, which triggers a rapid changing of Adblue dosage, and it aggravates the air quality that are caused by $NO_X$ emission and ammonia slip. In order to increase the conversion efficiency of $NO_X$ and avoid secondary pollution, the paper gives a comprehensive analysis of the SCR system and tells readers the key factors that affect time delay and RC characteristics. Accordingly, a map of time delay is established and a solution method for time constant and proportional constant is carried out. Finally, the paper accurately describes the input-output state relation of SCR system by using "variable RC model with time delay". The model can be used for a real-time correction of Adblue dosage, which can increase the conversion efficiency of $NO_X$ in SCR system and avoid secondary pollution forming. Obviously, the results of the work discover an avenue for the SCR control strategy.

Basic RF Characteristics of Fishbone-Type Transmission Line Employing Comb-Type Ground Plane (FTLCGP) on PES Substrate for Use in Flexible Passive Circuits

  • Yun, Young;Jeong, Jang-Hyeon;Kim, Hong Seung;Jang, Nakwon
    • ETRI Journal
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    • 제37권1호
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    • pp.128-137
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    • 2015
  • In this work, a fishbone-type transmission line employing a comb-type ground plane (FTLCGP) was fabricated on polyethersulfone (PES) substrate, and its RF characteristics were thoroughly investigated. According to the results, it was found that the FTLCGP on PES showed periodic capacitance values much higher than other types of transmission lines due to a coupling capacitance between the signal line and ground, which resulted in a reduction of wavelength and line width. Using the theoretical analysis, we also extracted the bandwidth characteristic of the FTLCGP on PES. According to the result, the FTLCGP structure showed a cut-off frequency of 280 GHz.

전자기 로렌쯔력을 이용한 박판성형 장비 개발 (Development of Sheet Metal Forming Apparatus Using Electromagnetic Lorentz Force)

  • 이현민;강범수;김정
    • 소성∙가공
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    • 제19권1호
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    • pp.38-43
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    • 2010
  • Electromagnetic forming (EMF) method is one of high-velocity forming processes, which uses electromagnetic Lorentz force. Advantages of this forming technique are summarized as improvement of formability, reduction in wrinkling, non-contact forming and applications of various forming process. In this study, the EMF apparatus is developed. It is designed to be stored in 10 capacitors connected in parallel, each with a capacitance of $50{\mu}F$ and maximum working voltage of 5kV. The system has capacitance of $500{\mu}F$ and maximum stored energy of 6.25kJ. And EMF experiments are carried out to verify the feasibility of the EMF apparatus, which has enough forming force from the results of EMF experiment. In addition, peak current carrying a forming coil is predicted from theoretical background, and verified the predicted value compared with experimental value using the current measurement equipment. Consequently, EMF apparatus developed in this study can be applied to various EMF researches for commercialization.

장파장 OEIC의 제작 및 특성 (Fabrication and Characteristics of Long Wavelength Receiver OEIC)

  • 박기성
    • 한국광학회:학술대회논문집
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    • 한국광학회 1991년도 제6회 파동 및 레이저 학술발표회 Prodeedings of 6th Conference on Waves and Lasers
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    • pp.190-193
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    • 1991
  • The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

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