• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.3
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• pp.146-153
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• 2006

We have been investigating InGaAs HEMTs as a future high-speed and low-power logic technology for beyond CMOS applications. In this work, we have experimentally studied the role of the side-recess spacing $(L_{side})$ on the logic performance of 50 nm $In_{0.7}Ga_{0.3}As$ As HEMTs. We have found that $L_{side}$ has a large influence on the electrostatic integrity (or short channel effects), gate leakage current, gate-drain capacitance, and source and drain resistance of the device. For our device design, an optimum value of $L_{side}$ of 150 nm is found. 50 nm $In_{0.7}Ga_{0.3}As$ HEMTs with this value of $L_{side}$ exhibit $I_{ON}/I_{OFF}$ ratios in excess of $10^4$, subthreshold slopes smaller than 90 mV/dec, and logic gate delays of about 1.3 ps at a $V_{CC}$ of 0.5 V. In spite of the fact that these devices are not optimized for logic, these values are comparable to state-of-the-art MOSFETs with similar gate lengths. Our work confirms that in the landscape of alternatives for beyond CMOS technologies, InAs-rich InGaAs FETs hold considerable promise.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.3
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• pp.311-320
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• 2008

In this paper, a new variable active inductor using a conventional grounded active inductor with feedback variable LC-resonator is proposed. The grounded active inductor is realized by the gyrator-C topology and the variable LC-resonator is realized by the low-Q spiral inductor and varactor. This variable LC-resonator can compensate the degradation of Q-factor due to parasitic capacitance of a transistor, and the frequency range with high Q-factor is adjustable by resonance frequency adjustment of LC-resonator. The fabricated variable active inductor with Magnachip $0.18{\mu}m$ CMOS process shows that high-Q frequency range can be adjusted according to varactor control voltage from 4.66 GHz to 5.45 GHz and Q-factor is higher than 50 in the operating frequency ranges. The measured inductance at 4.9GHz can be controlled from 4.12 nH to 5.97 nH by control voltage.

• The Journal of the Korea institute of electronic communication sciences
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• v.12 no.1
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• pp.209-218
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• 2017

Healthcare services can be provided through a number of independent service platforms for measurement of vital signs, diagnosis and prevention of diseases, and Information and communication technology(ICT) such as internet and mobile are converged to provide health information to users at anytime and anywhere, and it is in the center of the IoT(Internet of things). Accordingly, in this paper, we designed IoT based urination management system and evaluate the performance. A low - power Zigbee network was constructed for the configuration of the urination management system. The implemented capacitive diaper sensor was operable for the duration of 2,000 hours. We also built a database server using Raspberry Pi, a tiny embedded device, and stored the collected data to verify the data through an Android-based mobile application. The proposed urination management system can be utilized not only for the older patients, but also for the infants.

• Composites Research
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• v.31 no.5
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• pp.238-245
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• 2018

The hydrodynamic ram (HRAM) phenomenon is one of the main types of ballistic battle damages of a military aircraft and has great importance to airframe survivability design. The HRAM effect occurs due to the interaction between the fluid and structure, and damage can be investigated by measuring the pressure of the fluid and the dynamic strains on the structure. In this paper, HRAM test of a composite T-Joint was performed using a ram simulator which can generate HRAM pressure. In addition, calibration tests of PVDF sensor were performed to determine the circuit capacitance and time constant of the measurement system. The failure behavior of the composite T-Joint due to HRAM pressure was examined using the strain gauges and a PVDF sensor which were attached to the surface of the composite T-Joint.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.59-66
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• 2005

CMOS LC VCO for tri-bind wireless LAN applications was designed in 1.8V 0.18$\mu$m CMOS process. PMOS transistors were chosen for VCO core to reduce flicker noise. The possible operation was verified for 5.8GHz band (5.725$\~$5.825GHz), 5.2GHz band (5.150$\~$5.325GHz), and 2.4GHz band (2.412$\~$2.484GHz) using the switchable L-C resonators. To linearize its frequency-voltage gain (Kvco), optimized multiple MOS varactor biasing technique was used for capacitance linearization and PLL stability improvement. VCO core consumed 2mA current and $570{\mu}m{\times}600{\mu}m$ die area. The phase noise was lower than -110dBc/Hz at 1MHz offset for tri-band frequencies.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.12
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• pp.115-124
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• 2004

In this paper, we introduce the advanced compact transmission line with periodic stepped stubs. They are more effective than normal stubs in ATL. The short stepped stubs loading of transmission line work as effective shunt capacitance and that was proved by equivalent circuit based on transmission line theory and quasi-static analysis. And the compact branch-line coupler and the compact rat-race coupler via proposed compact microstrip line were designed at 1.8 ㎓. They have 677 ㎟ and 913 ㎟, respectively, and they are 62% and 45% of normal design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.18-27
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• 2010

In this paper, a 1.2V 7-bit 1GSPS A/D converter with offset self-calibration is proposed. The proposed A/D converter structure is based on the folding-interpolation whose folding rate is 2, interpolation rate is 8. Further, for the purpose of improving the chip performance, an offset self-calibration circuit is used. The offset self-calibration circuit reduce the variation of the offset-voltage，due to process mismatch, parasitic resistor, and parasitic capacitance. The chip has been fabricated with a 1.2V 65nm 1-poly 6-metal CMOS technology. The effective chip area is $0.87mm^2$ and the power dissipates about 110mW at 1.2V power supply. The measured SNDR is about 39.1dB when the input frequency is 250MHz at 800MHz sampling frequency. The measured SNDR is 3dB higher than the same circuit without any calibration.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1333-1338
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• 2008

In this paper, RF varactor diode are applied to the design of miniaturized and tunable bandstop filter. The proposed bandstop filter is based on a Defected Ground Structure(DGS) section topology. The designed tunable bandstop filter can achieve a significant size reduction by with loading capacitance component of varactor diode. It is observed from the measured results that the proposed tunable bandstop filter shows a wide tuning range of 42.9 % from 1.01 GHz to 1.99 GHz. The rejection level in the stopband is higher as the number of DGS section increases. In case of the proposed tunable bandstop filter with two DGS sections, the rejection level of the filter is better than 20 dB in the stopband during the tuning. In this case, the maximum insertion loss in the lower passband is 0.5 dB.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.48.2-48.2
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• 2010

The effect of additives as rare-earth in dielectric materials has been studied to meet the development trend in electronics on the miniaturization with increasing the capacitance of MLCCs (multi-layered ceramic capacitors). It was reported that the addition of rare-earth oxides in dielectrics would contribute to enhance dielectric properties and high temperature stability. Especially, dysprosium and thulium are well known to the representative elements functioned as selective substitution in barium titanate with perovskite structure. The effects of these additives on microstructure and electric properties were studied. The 0.8 mol% Dy doped $BaTiO_3$ and the 1.0 mol% Tm doped $BaTiO_3$ had the highest electric properties as optimized composition, respectively. According to the increase of rare-earth contents, the growth of abnormal grains was suppressed and pyrochlore phase was formed in more than solubility limits. Furthermore, the effect of two rare-earth elements co-doped $BaTiO_3$ on the dielectric properties and insulation resistance was investigated with different concentration. The dielectric specimens with $BaTiO_3-Dy_2O_3-Tm2O_3$ system were prepared by design of experiment for improving the electric properties and sintered at $1320^{\circ}C$ for 2h in a reducing atmosphere. The dielectric properties were evaluated from -55 to $125^{\circ}C$ (at $1KHz{\pm}10%$ and $1.0{\pm}0.2V$) and the insulation resistance was examined at 16V for 2 min. The morphology and crystallinity of the specimens were determined by microstructural and phase analysis.