• Journal of the Institute of Electronics Engineers of Korea SC
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• v.38 no.3
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• pp.31-39
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• 2001

In this paper, we proposed a new pixel circuit of the CMOS image sensor for high dynamic range operation, which is based on a multiple sampling scheme and a conditional reset circuit. To expand the pixel dynamic range, the output is multiple-sampled in the integration time. In each sampling, the pixel output is compared with a reference voltage, and the result of comparison may activate the conditional reset circuit. The times of conditional reset, N, during the integration will contribute to the increase of the dynamic range by the times of N. The test chip was fabricated with 0.65-${\mu}m$ CMOS technology (2-P, 2-M).

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.9
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• pp.13-19
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• 1999

This paper describes a design of an 8-bit 100KSPS 1mW CMOS A/D Converter. Using a novel systematic offset cancellation technique, we reduce the systematic offset voltage of operational amplifiers. Further, a new Gain amplifier is proposed. The proposed A/D Converter is fabricated with a $0.6{\mu}m$ single-poly triple-metal n-well CMOS technology. INL and DNL is within ${\pm}1LSB$, and SNR is about 43dB at the sampling frequency of 100KHz. The power consumption is $980{\mu}W$ at +3V power supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.25-29
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• 2002

There is an increasing interest in high-speed signal processing in modern telecommunication and SC circuit, HDTV, ISDN. There are many methods of high-speed signal processing. This paper describes a design approach for the realization of high-frequency Op-amp in CMOS technology. A limiting factor in Op-amp based analog integrated circuits is the limited useful frequency range. this thesis will develop a CMOS op-amp architecture with improved gainband width product with this technique an op-amp will achieve up to 170MHz (CL=2pF) unity-gain frequency with a 1.2-micron design rule. This CMOS op-amp is particularly suitable for achieving wide and stable closed-loop band widths, such as required in high-frequency SC filters, high-speed analog circuits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.3
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• pp.397-409
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• 1993

This paper proposed the design methodology of the 8 bit binary parallel adder with carry book-ahead scheme via current-mode CMOS multivalued logic and simulated the proposed adder under $5{\mu}m$ standard IC process technology. The threshold conditions of $G_K$ and $P_K$ which are needed for m-valued parallel adder with CLA are evaluated and adopted for quaternary logic. The design of quaternary CMOS logic circuits, encoder, decoder, mod-4 adder, $G_K$ and $P_K$ detecting circuit and current-voltage converter is proposed and is simulated to prove the operations. These circuits are necessary for binary arithmetic using multivalued logic. By comparing with the conventional binary adder and the CCD-MVL adder, We show that the proposed adder cab be designed one look-ahead carry generator with 1-level structure under standard CMOS technology and confirm the usefulness of the proposed adder.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.53-60
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• 2005

Recently, sub-micron CMOS technologies have taken the place of III-V materials in a number of areas in integrated circuit designs, in particular even for the applications of gjgabit optical communication applications due to its low cost, high integration level, low power dissipation, and short turn-around time characteristics. In this paper, a four-channel transimpedance amplifier (TIA) array is realized in a standard 0.35mm CMOS technology Each channel includes an optical PIN photodiode and a TIA incorporating the fully differential regulated cascode (RGC) input configuration to achieve effectively enhanced transconductance(gm) and also exploiting the inductive peaking technique to extend the bandwidth. Post-layout simulations show that each TIA demonstrates the mid-band transimpedance gain of 59.3dBW, the -3dB bandwidth of 2.45GHz for 0.5pF photodiode capacitance, and the average noise current spectral density of 18.4pA/sqrt(Hz). The TIA array dissipates 92mw p in total from a single 3.3V supply The four-channel RGC TIA array is suitable for low-power, high-speed optical interconnect applications.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1435-1435
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• 2015

광고 및 홍보의 마케팅 수단의 일환으로써 점포별로 QR코드를 사용하는 사례가 급격히 늘고 있다. 정보도트의 일종인 QR코드의 경우는 스마트폰과 더불어 홍보수단의 일환으로 활용되는 사례가 증가하고 있는 반면 QR코드는 정보를 표현할 수 있는 디자인의 범위가 좁고, 전송할 수 있는 Data의 용량이 적으며, 어두운 환경에서의 인식률이 저하되는 단점이 있다. 이에 기존의 QR코드 보다 다양한 디자인이 가능하고 대용량의 Data 전송이 가능한 컬러코드가 대두되고 있다. 컬러코드란 4가지 색상(빨강, 파랑, 초록, 검정)을 이용한 매트릭스 형태의 코드로 각종 디지털 정보를 저장하는 새로운 개념의 데이터 표현 기술이며, 이는 각 컬러에 디지털 정보를 매핑(mapping)하여 콘텐츠나 URL 등의 실제 정보들을 제공하는 역할을 하도록 설계되어 있다. 8MP CMOS센서기반 Colored LED Patch 인식 기법은 VLC에 포함되는 하나의 기술로서 차세대 조명 및 정보 디스플레이 장치로 각광을 받고 있는 반도체 조명 기술인 광원 정보 인식 기법이다. 따라서, 본 논문에서는 8MP CMOS센서 기반 컬러코드 LED Patch 인식 기법에 대해 제안하였다. 8MP CMOS 센서를 이용한 Colored LED Patch 인식 기법 중 하나로서 위치 정보 서비스 등 다양한 정보 획득이 가능하도록 연구하였으며, 동영상, 웹사이트 링크 등 여러 형식에 적용이 가능하도록 하였다. 본 연구에서 사용되는 8MP CMOS센서를 기반 Colored LED Patch 인식 기법을 통해 컬러코드는 코드 플랫폼으로 연결되어 콘텐츠의 위치를 파악하고 이용자에게 콘텐츠 및 정보가 전송된다. 이는 QR코드보다 높은 인식률로 빠르고 편리하게 정보를 제공할 수 있었다. 본 논문에서는 상기 제안 기술을 통하여 LED Patch의 높은 주목성과 가시성을 확보하여 보다 효과적인 광고 및 홍보의 시인성을 확보할 수 있다. 향후 본 제안기술을 통하여 사회 안전망을 위한 위치 및 정보 서비스 제공이 가능하며, 효과적인 광고 효과를 도출할 수 있을 것으로 사료된다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.259-262
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• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• Journal of Sensor Science and Technology
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• v.14 no.4
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• pp.272-277
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• 2005

A CMOS active pixel sensor has been designed and fabricated using standard 2-poly and 4-metal $0.35{\mu}m$ CMOS processing technology. The CMOS active pixel sensor has been made up of a unit pixel having a highly sensitive PMOSFET photo-detector and electronic shutters that can control the light exposure time to the PMOSFET photo-detector, correlated-double sampling (CDS) circuits, and an 8-bit two-step flash analog to digital converter (ADC) for digital output. This sensor can obtain a stable photo signal in a wide range of light intensity. It can be realized with a special function of an electronic shutter which controls the light exposure-time in the pixel. Moreover, this sensor had obtained the digital output using an embedded ADC for the system integration. The designed and fabricated image sensor has been implemented as a $128{\times}128$ pixel array. The area of the unit pixel is $7.60{\mu}m{\times}7.85{\mu}m$ and its fill factor is about 35 %.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.46-54
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• 1984

A silicon-gate n-well CMOS process with 3 $\mu$m gate length was developed and its possibility for the applications was discussed,. Threshold voltage was easily controlled by ion implantation and 3-$\mu$m gate length with 650 $\AA$ oxide shows ignorable short channel effect. Large value of Al-n+ contact resistance is one of the problems in fabrications of VLSI circuits. Transfer characteristics of CMOS inverter is fairly good and the propagation delay time per stage in ring oscillator with layout of (W/L) PMOS /(W/L) NMOS =(10/5)/(5/5) is about 3.4 nsec. catch-up occurs on substrate current of 3-5 mA in this process and critically dependent on the well doping density and nt-source to n-well space. Therefore, research, more on latch-up characteristics as a function of n-well profile and design rule, especially n+-source to n-well space, is required.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.262-266
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• 2011

A simulation study of a current-mode direct current (DC)-DC boost converter is presented in this paper. This converter, with a fully-integrated power module, is implemented by using bipolar complementary metal-oxide semiconductor (BiCMOS) technology. The current-sensing circuit has an op-amp to achieve high accuracy. With the sense metal-oxide semiconductor field-effect transistor (MOSFET) in the current sensor, the sensed inductor current with the internal ramp signal can be used for feedback control. In addition, BiCMOS technology is applied to the converter, for accurate current sensing and low power consumption. The DC-DC converter is designed with a standard 0.35 ${\mu}m$ BiCMOS process. The off-chip inductor-capacitor (LC) filter is operated with an inductance of 1 mH and a capacitance of 12.5 nF. Simulation results show the high performance of the current-sensing circuit and the validity of the BiCMOS converter. The output voltage is found to be 4.1 V with a ripple ratio of 1.5% at the duty ratio of 0.3. The sensing current is measured to be within 1 mA and follows to fit the order of the aspect ratio, between sensing and power FET.