• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.1551_1552
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• 2009

In this paper, we presented the packaging technologies of CMOS ISFET(Ion Sensitive Field Effect Transistor) pH sensor using post-CMOS process and MCP(Multi Chip Packaging). We have proposed and developed two types of packaging technology. one is one chip, which sensing layer is deposited on the gate metal of standard CMOS ISFET, the other is two chip type, which sensing layer is separated from CMOS ISFET and connected by bonding wire. These proposed packaging technologies would make it easy to fabricate CMOS ISFET pH sensor and to make variety types of pH sensor.

• 전자공학회논문지C
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• 제35C권12호
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• pp.40-48
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• 1998

본 논문에서는 rail-to-rail 복합입력단을 갖는 증폭회로의 옵셋전압을 보상해주기 위한 방법을 제안하고 집적회로로 구현하였다. 두 개의 보조증폭회로와 옵셋보상 커패시터들을 사용하여 NMOS 차동쌍과 PMOS 차동쌍의 옵셋을 각각 보상하고, ping-pong control을 사용하여 연속시간 동작이 가능한 3V rail-to-rail CMOS 증폭회로를 설계하였다. 설계된 증폭회로를 0.8㎛ single-poly double metal CMOS 공정으로 제작한 후 성능을 측정한 결과, 옵셋보상후의 옵셋전압은 옵셋보상전에 비해 약 20배정도 감소하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.206-211
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• 2005

The hearing aids specific operational amplifier described in this paper is a single-supply, low voltage CMOS amplifier. It works on 1.3V single-supply and gets a gain of 82dB. The 0.18${\mu}m$ CMOS process was chosen to reduce the driven voltage as well as the power dissipation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.244-247
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• 1999

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of a pair of transconductor and lowers supply voltage down to $V_{T}$+2 $V_{Ds,sat}$+ $V_{DS,triode}$. The designed analog four-quadrant multiplier have simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7 $V_{p-p}$././.

• 전자공학회논문지A
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• 제33A권6호
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• pp.239-247
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• 1996

The accuracy of sample-and-hold amplifiers (SHA's) empolying a CMOS process in limited by nonideal factors such as linearity errors of an op amp and feedthrough errors of switches. In this work, after some linearity improvement techniques for an op amp are discussed, three different SHA's for video signal processing are designed, simulated, and compared. The CMOS SHA design techniques with a 12-bit level accuracy are proposed by minimizing cirucit errors based on the simulated results.

• 센서학회지
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• 제27권3호
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• pp.160-164
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• 2018

In this paper, a wide dynamic range complementary metal-oxide-semiconductor (CMOS) image sensor with the adjustable sensitivity by using cascode metal-oxide-semiconductor field-effect transistor (MOSFET) and inverter is proposed. The characteristics of the CMOS image sensor were analyzed through experimental results. The proposed active pixel sensor consists of eight transistors operated under various light intensity conditions. The cascode MOSFET is operated as the constant current source. The current generated from the cascode MOSFET varies with the light intensity. The proposed CMOS image sensor has wide dynamic range under the high illumination owing to logarithmic response to the light intensity. In the proposed active pixel sensor, a CMOS inverter is added. The role of the CMOS inverter is to determine either the conventional mode or the wide dynamic range mode. The cascode MOSFET let the current flow the current if the CMOS inverter is turned on. The number of pixels is $140(H){\times}180(V)$ and the CMOS image sensor architecture is composed of a pixel array, multiplexer (MUX), shift registers, and biasing circuits. The sensor was fabricated using $0.35{\mu}m$ 2-poly 4-metal CMOS standard process.

• 한국정보통신학회논문지
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• 제15권4호
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• pp.897-904
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• 2011

본 논문에서는 CMOS 능동 인덕터를 이용하여 1.8GHz PCS 대역과 2.4GHz WLAN 대역에서 동조가 가능한 저잡음 증폭기의 새로운 회로구조를 제안하였다. CMOS 능동 인덕터 부하를 이용하는 저잡음 증폭기의 높은 잡음지수를 줄이기 위한 회로구조와 잡음지수를 더욱 감소시키기 위한 잡음상쇄기법을 적용하고 해석하였다. 이 동조가능 저잡음 증폭기를 $0.18{\mu}m$ CMOS 공정기술로 시뮬레이션을 수행한 결과는 잡음성능이 약 3.4dB 향상된 것을 보여주며, 이는 주로 제안된 새로운 회로구조에 기인한다.

• 정보처리학회논문지A
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• 제15A권5호
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• pp.243-248
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• 2008

본 논문은 다중 문턱전압 CMOS를 이용하여 저 전력 특성을 갖는 캐리 예측 가산기 (carry look-ahead adder)를 설계하였으며, 이를 일반적인 CMOS 가산기와 특성을 비교하였다. 전파 지연시간이 긴 임계경로에 낮은 문턱전압 트랜지스터를 사용하여 전파 지연시간을 감소시켰다. 전파 지연시간이 짧은 최단경로에는 높은 문턱전압 트랜지스터를 사용하여 회로전체의 소비전력을 감소시켰으며, 그 외의 논리블럭들은 정상 문턱전압의 트랜지스터를 사용하였다. 설계한 가산기는 일반적인 CMOS 회로와 비교하여 소비전력에서 14.71% 감소하였으며, 소비전력과 지연 시간의 곱에서 16.11%의 성능향상이 있었다. 이 회로는 삼성 $0.35{\mu}m$ CMOS 공정을 이용하여 설계하였으며, HSPICE를 통하여 검증하였다.

• Transactions on Electrical and Electronic Materials
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• 제10권2호
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(1)
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• pp.333-336
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• 2000

This paper describes a CMOS low noise amplifier (LNA) with bias current reusing architecture intended lot use in the front-end of IMT-2000 receiver. It has been implemented in a 0.35$\mu\textrm{m}$ CMOS process with two poly and four metal layers. In order to accuracy of simulation, we considered a bonding wire and a pad effect and used the measurements of capacitors and on-chip inductors which implemented in the same process. The LNA has a forward gain (S21) of 17 ㏈ and a noise fjgure of 1.26 ㏈. And it has a third-order intermodulation intercept point (IP3) of +3.15 ㏈m and a 1㏈ compression point (P1㏈) of -16 ㏈m, input referred, respectively. The power consumption is 19 ㎽ from a 3V supply.