• ETRI Journal
• /
• v.26 no.4
• /
• pp.307-314
• /
• 2004

The application of a discrete pseudomorphic high electron mobility transistor (p-HEMT) as a grounded switch allows for the development of low cost phase shifters and phase modulators operating in a Ku band. This fills the gap in the development of phase control devices comprising p-i-n diodes and microwave monolithic integrated circuits (MMICs). This paper describes a discrete p-HEMT characterization and modeling in switching mode as well as the development of a low-cost four-bit phase shifter and direct quadrature phase shift keying (QPSK) modulator. The developed devices operate in a Ku band with parameters comparable to commercially available MMIC counterparts. Both of them are CMOS compatible and have no power consumption. The parameters of the QPSK modulator are very close to the requirements of available standards for satellite earth stations.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.10
• /
• pp.844-850
• /
• 2002

Linearly graded profiles on the field area oxide are frequently used in power integrated circuits to reduce the surface electric field when power devices are operated in forward or reverse blocking modes. It is shown here that tapered windows can be made using the difference of etch rates between the bottom and the top layer of TEOS film. Annealed TEOS films are etched at a lower rate than the TEOS film without annealing Process. The fast etching layer results in window walls having slopes in the range of 25$^{\circ}$∼ 80$^{\circ}$ with respect to the wafer surface. Taper etching technique by annealing the TEOS film applies to high voltage LDMOS, which is compatible with CMOS process, due to the minimum changes in both of design rules and thermal budget.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2002.08a
• /
• pp.325-328
• /
• 2002

We developed a high performance 2.2" active matrix OLED display for IMT-2000 mobile phone. Scan and Data driver circuits were integrated on the glass substrate, using low temperature poly-Si(LTPS) TFT CMOS technology. High efficiency EL materials were employed to the panel for low power consumption. Peak luminescence of the panel was higher than 250cd/$m^2$ with power consumption of 200mW.

• Proceedings of the KSR Conference
• /
• 1998.05a
• /
• pp.408-418
• /
• 1998

This paper presents the implementation of comparator which is self-testing with respect to the faults caused by any single physical defect likely to occur in NMOS and CMOS integrated circuit. The goal is to use it for the fault-tolerant system. First, a new fault model for PLA(Programmable Logic Array) is presented. This model reflects several physical defects in VLSI circuits. It focuses on the designs based on PLA because VLSI chips are far too complex to allow detailed analysis of all the possible physical defects that can occur and of the effects on the operation of the circuit. Second, this paper shows that these design, which has been implemented with 2 level AND-ORor NOR-NOR circuit, are optimal in term of size. And it also presents a formal proof that a comparator implemented using NOR-NOR PLA, based on these design, is sol f-testing with respect to most single faults in the presented fault model. Finally, it discusses the application of the self-testing comparator as a building block for the implementation of the fault-tolerant system.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.661-662
• /
• 2006

This paper introduces a CMOS clock driver that shows a high efficiency of electric power (lower power consumption) with the supply of lower voltage(VDD), by taking advantage of charge recycling technology. Comparing with the existing structure, this driver showed the improved maximum efficiency of electric power; 72% and 68%, with the supplied voltage of 1.8v and 1.2v, respectively. Since the output waveform shows the tri-state operating region, utilization is expected in the digital integrated circuits.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.2
• /
• pp.170-183
• /
• 2013

This paper gives an overview of fractional-N phase-locked loops (PLLs) with practical design perspectives focusing on a ${\Delta}{\Sigma}$ modulation technique and a finite-impulse response (FIR) filtering method. Spur generation and nonlinearity issues in the ${\Delta}{\Sigma}$ fractional-N PLLs are discussed with simulation and hardware results. High-order ${\Delta}{\Sigma}$ modulation with FIR-embedded filtering is considered for low noise frequency generation. Also, various architectures of finite-modulo fractional-N PLLs are reviewed for alternative low cost design, and the FIR filtering technique is shown to be useful for spur reduction in the finite-modulo fractional-N PLL design.

• Proceedings of the Korean Magnestics Society Conference
• /
• 2000.09a
• /
• pp.5-32
• /
• 2000

MRAM, High performance MRAM using MTJS demostrated, fully integrated MTJ MRAM with CMOS circuits, write time ~2.3 nsec; read time ~3 nsec, Thermally stable up to ~350 C, Switching field distibution controlled by size & shape. Magnetic Tunnel Junction Properties, Magnetoresistance: ~50% at room temperature, enhanced by thermal treatment, Negative and Positive MR by interface modification, Spin Polarization: >55% at 0.25K, Insensitive ot FM composition, Resistance $\times$ Area product, ranging from ~20 to 10$^{9}$ $\Omega$(${\mu}{\textrm}{m}$)$^{2}$, Spin valve transistor, Tunnel injected spin polarization for "hot" electrons, Decrease of MTJMR at high bias originates from anode.

• Transactions on Electrical and Electronic Materials
• /
• v.7 no.4
• /
• pp.173-179
• /
• 2006

Due to the limitations of the channel length, the lateral spread for two-dimensional impurity distributions is critical for the analysis of devices including the integrated complementary metal oxide semiconductor (CMOS) circuits and high frequency semiconductor devices. The developed codes were then compared with the two-dimensional implanted profiles measured by transmission electron microscope (TEM) as well as simulated by a commercial TSUPREM4 for verification purposes. The measured two-dimensional TEM data obtained by chemical etching-method was consistent with the results of the developed analytical model, and it seemed to be more accurate than the results attained by a commercial TSUPREM4. The developed codes can be applied on a wider energy range $(1KeV{\sim}30MeV)$ than a commercial TSUPREM4 of which the maximum energy range cannot exceed 1MeV for the limited doping elements. Moreover, it is not only limited to diffusion process but also can be applied to implantation due to the sloped and nano scale structure of the mask.

• ETRI Journal
• /
• v.44 no.3
• /
• pp.491-503
• /
• 2022

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are continuously scaling down in the nanoscale region to improve the functionality of integrated circuits. The scaling down of MOSFET devices causes short-channel effects in the nanoscale region. In nanoscale region, leakage current components are increasing, resulting in substantial power dissipation. Very large-scale integration designers are constantly exploring different effective methods of mitigating the power dissipation. In this study, a transistor-level input-controlled stacking (ICS) approach is proposed for minimizing significant power dissipation. A low-power ICS approach is extensively discussed to verify its importance in low-power applications. Circuit reliability is monitored for process and voltage and temperature variations. The ICS approach is designed and simulated using Cadence's tools and compared with existing low-power and high-speed techniques at a 22-nm technology node. The ICS approach decreases power dissipation by 84.95% at a cost of 5.89 times increase in propagation delay, and improves energy dissipation reliability by 82.54% compared with conventional circuit for a ring oscillator comprising 5-inverters.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.7 no.4
• /
• pp.715-720
• /
• 2012

This study presents a hybrid balanced voltage controlled oscillator (VCO) circuit which is suitable for low phase noise operation at sub-1V supply voltages. Half circuits of the proposed VCO use the varactor-integrated feedback capacitors in their respective circuit. The varactor-integrated feedback capacitors further increase the negative resistance of the equivalent tank thereby ensuring stable start-up of oscillation even at the sub-1V supply voltage. In addition, this work theoretically analyses the phenomenon of the increase of the negative resistance. Simulation results using a $0.18{\mu}m$ RF CMOS technology exhibit the phase noises of -122.4 to -125.5.8 dBc/Hz at 1 MHz offset from oscillation frequency of 4.87 GHz over the supply voltages of 0.6 through 0.9 V.