• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.497-502
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• 2007

Broadband monolithic SiGe HBT variable gain amplifier with a feedforward configuration have been newly developed to improve bandwidth and dB-linearly controlled gain characteristics. The VGA has been implemented in a $0.35-{\mu}m$ BiCMOS process. The VGA achieves a dynamic gain-control range of 19.6 dB and a 3-dB bandwidth of 4 GHz ($4{\sim}8\;GHz$) with the control-voltage range from 0.6 to 2.6 V. The VGA produces a maximum gain of 9.3 dB at 6 GHz and a output power of -3 dBm at 8 GHz.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.7
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• pp.34-41
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• 1999

In this paper, hot carrier induced performance degradation of peripheral circuits in memory devices such as static type imput buffer, latch type imput buffer and sense amplifier circuit has been measured and analyzed. The used design and fabrication of the peripheral circuits were $0.8 {\mu}m$ standard CMOS process. The analysis method is to find out which device is most significantly degraded in test circuits by using spice simulation, and then to characterize the correlation between device and circuit performance degradation. From the result of the performance degradation of static type input buffer, the trip point was increased due to the transconductance degradation of NMOS. In the case of latch type input buffer, there was a time delay due to the transconductance degradation of NMOS device. Finally, hot carrier induced the decrease of half-Vcc voltage and the increased of sensing voltage in sense amplifier circuits have been measured.

• Journal of Sensor Science and Technology
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• v.8 no.2
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• pp.163-170
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• 1999

A programmable A/D converter for an embedded fiber-optic combustion pressure sensor has been designed with 8 N and P channel MOSFETs, respectively. A local field enhancement for reducing programming voltage during writing as well as erasing an EEPROM device is introduced. In order to observe linear programmability of the EEPROM device during programming mode, a cell is developed with a $1.2\;{\mu}m$ double poly CMOS fabrication process in MOSIS. It is observed that the high resolution, of say 10mVolt, is valid in the range 1.25volts to 2volts. The experimental result is used for simulating the programmable 8 bit A/D converter with Hspice. The A/D converter is demonstrated to consume low power, $37\;{\mu}W$ by utilizing a programming operation. In addition, the converter is attained at the conversion frequency of 333 MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.127-132
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• 2012

In this paper, the edge effects of proposed structure in active region for high voltage in shallow trench isolation for very large integrated MOSFET were simulated. Shallow trench isolation (STI) is a key process component in CMOS technologies because it provides electrical isolation between transistors and transistors. As a simulation results, shallow trench structure were intended to be electric functions of passive, as device dimensions shrink, the electrical characteristics influence of proposed STI structures on the transistor applications become stronger the potential difference electric field and saturation threshold voltage.

• ETRI Journal
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• v.38 no.4
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• pp.685-694
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• 2016

A surface micromachined piezoresistive pressure sensor with a novel internal substrate vacuum cavity was developed. The proposed internal substrate vacuum cavity is formed by selectively etching the silicon substrate under the sensing diaphragm. For the proposed cavity, a new fabrication process including a cavity side-wall formation, dry isotropic cavity etching, and cavity vacuum sealing was developed that is fully CMOS-compatible, low in cost, and reliable. The sensitivity of the fabricated pressure sensors is 2.80 mV/V/bar and 3.46 mV/V/bar for a rectangular and circular diaphragm, respectively, and the linearity is 0.39% and 0.16% for these two diaphragms. The temperature coefficient of the resistances of the polysilicon piezoresistor is 0.003% to 0.005% per degree of Celsius according to the sensor design. The temperature coefficient of the offset voltage at 1 atm is 0.0019 mV and 0.0051 mV per degree of Celsius for a rectangular and circular diaphragm, respectively. The measurement results demonstrate the feasibility of the proposed pressure sensor as a highly sensitive circuit-integrated pressure sensor.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.127-132
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• 2019

In this study, the fabrication of through-silicon vias (TSVs) filled with SWNTs/Sn by utilizing surface/bulk micromachining and MEMS technologies is proposed. Tin (Sn) and single-walled nanotube (SWNT) powders are used as TSV interconnector materials in the development of a novel TSV at low temperature. The measured resistance of a TSV filled with SWNT/Sn powder is considerably reduced by increasing the fraction of Sn and is lower than that of a TSV filled with only Sn. This is because of a decrease in the surface scattering of electrons along with an increase in the grain size of sintered SWNTs/Sn. The proposed method is conducted at low temperatures (< $400^{\circ}C$) due to the low melting temperature of Sn; hence, the proposed TSVs filled with SWNTs/Sn can be utilized in CMOS based applications.

• Journal of Sensor Science and Technology
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• v.11 no.3
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• pp.163-170
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• 2002

This paper proposes a $10\;{\mu}m$ thick oxide air-bridge structure which can be used as a substrate for RF circuits. The structure was fabricated by anodic reaction, complex oxidation and micromachining technology using TMAH etching. High quality films were obtained by combining low temperature thermal oxidation ($500^{\circ}C$, 1 hr at $H_2O/O_2$) and rapid thermal oxidation (RTO) process ($1050^{\circ}C$, 2 min). This structure is mechanically stable because of thick oxide layer up to $10\;{\mu}m$ and is expected to solve the problem of high dielectric loss of silicon substrate in RF region. The properties of the transmission line formed on the oxidized porous silicon (OPS) air-bridge were investigated and compared with those of the transmission line formed on the OPS layers. The insertion loss of coplanar waveguide (CPW) on OPS air-bridge was (about 2dB) lower than that of CPW on OPS layers. Also, the return loss of CPW on OPS air-bridge was less than about -20 dB at measured frequency region for 2.2 mm. Therefore, this technology is very promising for extending the use of CMOS circuitry to higher RF frequencies.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1747-1754
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• 2016

This paper presents a high accuracy and fast hybrid on-chip temperature sensor. The proposed temperature sensor combines a SAR type temperature sensor with a ${\Sigma}{\Delta}$ type temperature sensor. The SAR type temperature sensor has fast temperature searching time but it has more error than the ${\Sigma}{\Delta}$ type temperature sensor. The ${\Sigma}{\Delta}$ type temperature sensor is accurate but it is slower than the SAR type temperature sensor. The proposed temperature sensor uses both the SAR and ${\Sigma}{\Delta}$ type temperature sensors, so that the proposed temperature sensor has high accuracy and fast temperature searching. Also, the proposed temperature sensor includes a temperature error compensating circuit by storing the temperature errors in a memory circuit after chip fabrication. The proposed temperature sensor was fabricated in 3.3V CMOS $0.35{\mu}m$ process. Its temperature resolution, power consumption, and area are $0.15^{\circ}C$, $540{\mu}W$, and $1.2mm^2$, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1C
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• pp.102-110
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• 2004

In this paper, we propose a VLSI structure of real-time image compression and reconstruction processor using 2-D discrete wavelet transform and implement into a hardware which use minimal hardware resource using ASIC library. In the implemented hardware, Data path part consists of the DWT kernel for the wavelet transform and inverse transform, quantizer/dequantizer, the huffman encoder/huffman decoder, the adder/buffer for the inverse wavelet transform, and the interface modules for input/output. Control part consists of the programming register, the controller which decodes the instructions and generates the control signals, and the status register for indicating the internal state into the external of circuit. According to the programming condition, the designed circuit has the various selective output formats which are wavelet coefficient, quantization coefficient or index, and Huffman code in image compression mode, and Huffman decoding result, reconstructed quantization coefficient, and reconstructed wavelet coefficient in image reconstructed mode. The programming register has 16 stages and one instruction can be used for a horizontal(or vertical) filtering in a level. Since each register automatically operated in the right order, 4-level discrete wavelet transform can be executed by a programming. We synthesized the designed circuit with synthesis library of Hynix 0.35um CMOS fabrication using the synthesis tool, Synopsys and extracted the gate-level netlist. From the netlist, timing information was extracted using Vela tool. We executed the timing simulation with the extracted netlist and timing information using NC-Verilog tool. Also PNR and layout process was executed using Apollo tool. The Implemented hardware has about 50,000 gate sizes and stably operates in 80MHz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.