1 |
Chen-Yu Hsieh, et al "Distinguishing Between STI Stress and Delta Width in Gate Direct Tunneling Current of n-MOSFETs" IEEE ED Letters, Vol. 30, No. 5, pp. 529-531, May, 2009
DOI
ScienceOn
|
2 |
V. C. Su et al "Shallow-Trench-Isolation(STI)- Induced Mechanical-Stress-Related Kink- Effect Behaviors of 40-nm PD SOI NMOS Device" IEEE Trans. on Electron Devices, Vol. 55, No. 6, pp. 1588-1562, June 2008
|
3 |
A. Asenov et al "Simulation of Statistical Aspects of Charge Trapping and Related Degradation in Bulk MOSFETs in the Presence of Random Discrete Dopants" IEEE Trans. on ED, Vol. 57, No. 4, pp. 795-803, April 2010
DOI
ScienceOn
|
4 |
Andrew B. Kahng., et al "Exploiting STI Stress for Performance" 2007 IEEE IEDM, pp. 83-90, Dec., 2007
|
5 |
Jiying Xue et al. "A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization" IEEE Trans. ED on Very Large Scale Integration (VLSI) Systems pp. 1-13, 2011
|