• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.408-414
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• 2014

This paper proposes a charge-pump phase-locked loop (PLL) with 51-phase output clock of a 125 MHz target frequency. The proposed PLL uses three voltage controlled oscillators (VCOs) to generate 51-phase clock and increase of maximum operating frequency. The 17 delay-cells consists of each VCO, and a resistor averaging scheme which reduces the phase mismatch among 51-phase clock combines three VCOs. The proposed PLL uses a 65 nm 1-poly 9-metal CMOS process with 1.0 V supply. The simulated peak-to-peak 지터 of output clock is 0.82 ps at an operating frequency of 125 MHz. The differential non-linearity (DNL) and integral non-linearity (INL) of the 51-phase output clock are -0.013/+0.012 LSB and -0.033/+0.041 LSB, respectively. The operating frequency range is 15 to 210 MHz. The area and power consumption of the implemented PLL are $580{\times}160{\mu}m^2$ and 3.48 mW, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.691-698
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• 2008

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.322-329
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• 2007

A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has been designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.330-336
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• 2007

A single pixel photon counting type image sensor which is applicable for medical diagnosis with digitally obtained image and industrial purpose has tern designed with $0.18{\mu}m$ triple-well CMOS process. The designed single pixel for readout chip is able to be operated by single supply voltage to simplify digital X-ray image sensor module and a preamplifier which is consist of folded cascode CMOS operational amplifier has been designed to enlarge signal voltage(${\Delta}Vs$), the output voltage of preamplifier. And an externally tunable threshold voltage generator circuit which generates threshold voltage in the readout chip has been newly proposed against the conventional external threshold voltage supply. In addition, A dark current compensation circuit for reducing dark current noise from photo diode is proposed and 15bit LFSR(Linear Feedback Shift Resister) Counter which is able to have high counting frequency and small layout area is designed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.807-815
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• 2019

In this paper, we design a power amplifier to support quad-band in wireless communication devices using RF CMOS 180-nm process. The proposed power amplifier consists of low-band 0.9, 1.8, and 2.4 GHz and high-band 5 GHz. We proposed a structure that can support each input matching network without using a switch. For maximum linear output power, the output matching network was designed for impedance conversion to the power matching point. The fabricated quad-band power amplifier was verified using modulation signals. The long-term evolution(LTE) 10 MHz modulated signal was used for 0.9 and 1.8 GHz, and the measured output power is 23.55 and 24.23 dBm, respectively. The LTE 20 MHz modulated signal was used for 1.8 GHz, and the measured output power is 22.24 dBm. The wireless local area network(WLAN) 802.11n modulated signal was used for 2.4 GHz and 5.0 GHz. We obtain maximum linear output power of 20.58 dBm at 2.4 GHz and 17.7 dBm at 5.0 GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.10a
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• pp.527-530
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• 2016

This paper presents curvature-compensated reference circuits operating under low-voltage condition and achieving low-power consumption with $0.35-{\mu}m$ standard CMOS process. The proposed circuit can operate under less than 1-V supply voltage by using MOS transistors operating in weak-inversion region. The simulation results shows a low temperature coefficient by using the proposed curvature compensation technique. It generates a graph-shape temperature characteristic that looks like a sine curve, not a bell-shape characteristic presented in other published BGRs without curvature compensation. The proposed circuits operate with 0.9-V supply voltage. First, the voltage reference circuit consumes 176nW power and the temperature coefficient is $26.4ppm/^{\circ}C$. The current reference circuit is designed to operate with 194.3nW power consumption and $13.3ppm/^{\circ}C$ temperature coefficient.

• Journal of IKEEE
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• v.23 no.3
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• pp.858-864
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• 2019

A clock system is proposed to eliminate data loss due to frequency difference between sensor nodes in a sensor utility network. The proposed clock system for each sensor node consists of a bust clock-data recovery (CDR) circuit, a digital phase-locked loop outputting a 32-phase clock, and a digital frequency synthesizer using a programmable open-loop fractional divider. A CMOS oscillator using an active inductor is used instead of a burst CDR circuit for the first sensor node. The proposed clock system is designed by using a 65 nm CMOS process with a 1.2 V supply voltage. When the frequency error between the sensor nodes is 1%, the proposed burst CDR has a time jitter of only 4.95 ns with a frequency multiplied by 64 for a data rate of 5 Mbps as the reference clock. Furthermore, the frequency change of the designed digital frequency synthesizer is performed within one period of the output clock in the frequency range of 100 kHz to 320 MHz.

• Journal of IKEEE
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• v.25 no.2
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• pp.302-308
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• 2021

A 12-bit 10-MS/s pipeline analog-to-digital converter (ADC) is proposed for image processing applications. The proposed pipeline ADC consists of a sample and hold amplifier, three stages, a 3-bit flash analog-to-digital converter, and a digital error corrector. Each stage is operated by using a 4-bit flash ADC (FADC) and a multiplying digital-to-analog converter (MDAC). The proposed sample and hold amplifier increases the voltage gain using gain boosting for the ADC with high resolution. The proposed pipelined ADC is designed using a 180-nm CMOS process with a supply voltage of 1.8 and it has an effective number of bit (ENOB) of 10.52 bits at sampling rate of 10MS/s for a 1-V_pp differential sinusoidal analog input with frequency of 1 MHz. The measured ENOB is 10.12 bits when the frequency of the sinusoidal analog input signal is a Nyquist frequency of approximately 5 MHz.

• The Journal of the Korea institute of electronic communication sciences
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• v.7 no.5
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• pp.1061-1066
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• 2012

A digital memory has been widely used as a device for storing information due to its reliable, fast and relatively simple control circuit. However, the storage of the digital memory will be limited by the inablility to make smaller linewidths. One way to dramatically increase the storeage capability of the memory is to change the type of stored data from digital to analog. The analog memory fabricated in a standard single poly 0.6um CMOS process has been developed. Single cell and adjacent circuit block for programming have been designed and characterized. Applications include low-density non-volatile memory, control of redundancy in SRAM and DRAM memories, ID or security code registers, and image and sound memory.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.175-183
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• 2014

In this paper, we present the design and implementation of real-time sound localization based on $0.13{\mu}m$ CMOS process. Time delay of arrival (TDOA) estimation was used to obtain the direction of the sound signal. The sound localization chip consists of four modules: data buffering, short-term energy calculation, cross correlation, and azimuth calculation. Our chip achieved real-time processing speed with full range ($360^{\circ}$) using three microphones. Additionally, we developed a dedicated sound localization circuit (DSLC) system for measuring the accuracy of the sound localization chip. The DSLC system revealed that our chip gave reasonably accurate results in an experiment that was carried out in a noisy and reverberant environment. In addition, the performance of our chip was compared with those of other chip designs.