• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.6
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• pp.425-432
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• 2004

In this paper, we introduce the analog memory fabricated in a 0.35${\mu}{\textrm}{m}$ single poly standard CMOS process. We measured the programming characteristics of the analog memory cell such as linearity, reliability etc. Finally, we found that the characteristics of the programming of the cell depend on the magnitude and the width of the programming pulse, and that the accuracy of the programming within 10mV is feasible under the optimal condition. In order to standardize the characteristics of the cell, we have investigated numbers of cells. Thus we have used a program named Labview and a data acquisition board to accumulate the data related to the programming characteristics automatically.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.5
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• pp.421-425
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• 2008

In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a $0.35\;{\mu}m$ CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.102-103
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• 2007

The electrical characteristics of high power LIGBT implemented by CMOS process are described and compared with those of high voltage LDMOSFET with the same device dimensions. LIGBT has exhibited approximately 8 times superior current drive capability than LDMOSFET. The proposed p+/n+ anode structure resulted in the significant increase of on-state breakdown voltage of LIGBT. Therefore, LIGBT suggested in this paper is one of the promising candidate for smart power IC applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.11a
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• pp.443-446
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• 2003

A 2-Dimensional SSIMT(Suppressed Sidewall Injection Magnetotransistor) sensor with high linearity is presented in this paper. The prototype is fabricated by using the Hynix $0.6{\mu}m$ CMOS Process. The fabricated SSIMT shows that the variation of each collectors current are extremely linear by varing the magnetic induction from -200mT to 200mT at $I_B\;:\;1000{\mu}A,\;V_{CE}\;=\;5V\;and\;V_{SUB}\;=\;5V$. The relative sensitivity is up to 13%/T. At B = 0, magnetic offset is about 40mT, there relative sensitivity is 4.72%/T. The nonlinearity of the fabricated 2-D SSIMT is measured about 1.2%.

• Electronics and Telecommunications Trends
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• v.33 no.6
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• pp.1-11
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• 2018

Several industrial applications such as space exploration, aerospace, automotive, the downhole oil and gas industry, and geothermal power plants require specific electronic systems under extremely high temperatures. For the majority of such applications, silicon-based technologies (bulk silicon, silicon-on-insulator) are limited by their maximum operating temperature. Silicon carbide (SiC) has been recognized as one of the prime candidates for providing the desired semiconductor in extremely high-temperature applications. In addition, it has become particularly interesting owing to a Si-compatible process technology for dedicated devices and integrated circuits. This paper briefly introduces a variety of SiC-based integrated circuits for use under extremely high temperatures and covers the technology trend of SiC CMOS devices and processes including the useful implementation of SiC ICs.

• Journal of Sensor Science and Technology
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• v.11 no.5
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• pp.255-262
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• 2002

Human retina is able to detect the edge of an object effectively. We designed a CMOS vision chip by modeling cells of the retina as hardwares involved in edge detection. There are several fluctuation factors which affect characteristics of MOSFETs during CMOS fabrication process and this effect appears as output offset of the vision chip which is composed of pixel arrays and readout circuits. The vision chip detecting edge information from input image is used for input stage of other systems. Therefore, the output offset of a vision chip determine the efficiency of the entire performance of a system. In order to eliminate the offset at the output stage, we designed a vision chip by using CDS(Correlated Double Sampling) technique. Using standard CMOS process, it is possible to integrate with other circuits. Having reliable output characteristics, this chip can be used at the input stage for many applications, like targe tracking system, fingerprint recognition system, human-friendly robot system and etc.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.56-62
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• 2013

We present a rectifier for wireless power transmission using multiplier configuration in layout for MOSFETs which works at 13.56 MHz, designed to fit in CMOS process where conventionally used diodes are replaced with the cross-coupled MOSFETs. Full bridge rectifier structure without comparators is employed to reduce current consumption and to be working up to higher frequency. Multiplier configuration designed in layout reduces time delay originated from parasitic series resistance and shunt capacitance at each finger due to long connecting layout, leading to fast transition from on-state to off-state cross-coupled circuit structure and vice versa. The power conversion efficiency is significantly increased due to this fast transition time. The rectifier is fabricated in $0.11{\mu}m$ CMOS process, RF to DC power conversion efficiency is measured as 86.4% at the peak, and this good efficiency is maintained up to 600 MHz, which is, to our best knowledge, the highest frequency based on cross-coupled configuration.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.128-133
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• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.46-54
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• 1984

A silicon-gate n-well CMOS process with 3 $\mu$m gate length was developed and its possibility for the applications was discussed,. Threshold voltage was easily controlled by ion implantation and 3-$\mu$m gate length with 650 $\AA$ oxide shows ignorable short channel effect. Large value of Al-n+ contact resistance is one of the problems in fabrications of VLSI circuits. Transfer characteristics of CMOS inverter is fairly good and the propagation delay time per stage in ring oscillator with layout of (W/L) PMOS /(W/L) NMOS =(10/5)/(5/5) is about 3.4 nsec. catch-up occurs on substrate current of 3-5 mA in this process and critically dependent on the well doping density and nt-source to n-well space. Therefore, research, more on latch-up characteristics as a function of n-well profile and design rule, especially n+-source to n-well space, is required.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.141-147
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• 2008

This paper describes the design of frequency down converting Mixer in the receiver to use compound semiconductor and CMOS product process. The basic theory and structure of frequency down converting Mixer is surveyed, and we design mixer circuit with active balun which use the compound semiconductor and CMOS process. This mixer convert a single ended signal to differential signal at input port of RF and LO instead of matching circuit to get dual band balanced mixer structure and characteristic broadband. This designed mixer has a conversion gain $-1{\sim}-6[dB]$ at $2{\sim}6[GHz]$ bandwidths. However, the simulation of the designed mixer with active balun has the result of a 7[dB] conversion gain for -2[dBm] LO input power and -10[dBm] input P1[dB] at 5.8[GHz].