• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.8-14
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• 2008

A fully CMOS-integrated carbon nanotube (CNT) sensor array is proposed. After the sensor chip is fabricated in commercial CMOS process, the CNTs network is formed on the top of the fabricated sensor chip through the room-temperature post-CMOS processes. When the resistance of the CNT is changed by the chemical reaction, the read-out circuit in the chip measures the charging time of the $R_{CNT}$-Capacitor. finally the information of measured frequency is converted to a digital code. The CMOS sensor chip was fabricated by standard 0.18um technology and the size of the $8{\times}8$ sensor array is $2mm{\times}2mn$. We have carried out an experiment detecting the biochemical material, glutamate, using this sensor chip. From the experiment the CMOS sensor chip shows the feasibility of sensor for the simultaneous detection of the various target materials.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.8
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• pp.399-403
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• 2006

An accurate constant output voltage provided by the analog memory cell may be used by the low power oscillator to generate an accurate low frequency output signal. This accurate low frequency output signal may be used to maintain long-term timing accuracy in host devices during sleep modes of operation when an external crystal is not available to provide a clock signal. Further, incorporation of the analog memory cell in the low power oscillator is fully implementable in a 0.35um Samsung standard CMOS process. Therefore, the analog memory cell incorporated into the low power oscillator avoids the previous problems in a oscillator by providing a temperature-stable, low power consumption, size-efficient method for generating an accurate reference clock signal that can be used to support long sleep mode operation.

• Journal of electromagnetic engineering and science
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• v.3 no.1
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• pp.29-34
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• 2003

In this paper, we fabricated an 1.8 ㎓ differential VCO using a commercial 0.5 ${\mu}{\textrm}{m}$ SiGe BiCMOS process technology, The fabricated VCO consumes 16 ㎃ at 3 V supply voltage and has a 1.2 $\times$ 1.6 $mm^2$TEX>chip area. A phase noise measured at 100 KHz offset carrier is -110 ㏈c/Hz and a tuning range is 1795 MHz~1910 MHz when two varactor diodes are biased from 0 V to 3 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.535-541
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• 2016

A low phase noise META-VCO based-on meta-structure was designed using 65 nm CMOS process. We used a meta-structure to get good phase noise characteristics. The measured phase noises are -67.8 dBc/Hz, -96.37 dBc/Hz, and -107.37 dBc/Hz at 100 kHz, 1 MHz, and 10 MHz offset respectively. The META-VCO operates 8.45~8.77 GHz according to VCTRL, and the output power is -19.12 dBm. The power consumption is 28 mW with 1.2-V supply voltage. The calculated FOM is -140.76 dBc/Hz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.168-171
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• 2002

A SSIMT(Suppressed Sidewall Injection Magnetotransistor) sensor with high linearity is presented in this thesis. The prototype is fabricated by using the Hynix 0.6$\mu\textrm{m}$ P-substrate twin-well double poly three-metal CMOS Process. The fabricated SSIMT shows that variation of the collector current is extremely linear by varing the magnetic induction from -200mT to 200mT at I$\_$B/=500${\mu}$A, V$\_$CE/=2V and V$\_$SUB/=5V. The relative sensitivity is up to 120%/T. At B = 0, magnetic offset is about 79mT, there relative sensitivity is 30.5%/T. The nonlinearity of the fabricated SSIMT is measured about 1.4%.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.51-54
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• 2000

This paper presents an efficient method for estimating maximum simultaneous switching noise(SSN) of ground interconnection networks in CMOS systems. For the derivation of maximum SSN expression we use ａ-power law MOS model and an iterative method to reduce error that may occur due to the assumptions used in the derivation process. The accuracy of the proposed method is verified by comparing the results with those of previous researches and HSPICE simulations under the present process parameters and environmental conditions. Our method predicts the maximum SSN values more accurately as compared to existing approaches even in more practical cases such that there exist some of output drivers not in transition.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.10
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• pp.881-886
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• 2003

This paper describes the design and implementation of a passive transponder chip for RFID applications. Passive transponders do not have their own power supply, and therefore all power required for the operation of a passive transponder must be drawn from the field of the reader. The designed transponder consists of a full wave rectifier to generate a dc supply voltage, a 128-bit mask ROM to store the information, and Manchester coding and load modulation circuits to be used for transmitting the information from the transponder to the reader. The transponder with a size 410 x 900 ${\mu}$m$^2$ has been fabricated using 0.65 ${\mu}$m 2-poly, 2-metal CMOS process. The measurement results show the data transmission rate of 3.9 kbps at RF frequency 125 kHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.1
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• pp.59-67
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• 1990

In this paper, BLC adder/subtractor and MTG adder which can be used as a fundamental operation block in VLSI processors are designed, and their structural and electrical characteristics are analyzed and compared. Also, two circuits are fabricated usign 2\ulcorner CMOS process and their time delays for critical paths are measured. For 8 bit binary addition, the measured critical delays for MSB sum of the BLC adder/subtractor are 26 nsec for rising delay and 32nsec for falling. Those for MSB carry out of the MTG adder are 28nsed and 38nsec, respectively. The BLC adder/subtractor has a layout area which is 4 times larger than the MTG adder, and a fast operation speed. On the contrary, the MTG adder has a small layout area and a large time delay.

• ETRI Journal
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• v.31 no.6
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• pp.755-764
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• 2009

This paper presents a switched self-biasing and a tail current-shaping technique to suppress the 1/f noise from a tail current source in differential cross-coupled inductance-capacitance (LC) voltage-controlled oscillators (VCOs). The proposed LC VCO has an amplitude control characteristic due to the creation of negative feedback for the oscillation waveform amplitude. It is fabricated using a 0.13 ${\mu}m$ CMOS process. The measured phase noise is -117 dBc/Hz at a 1 MHz offset from a 4.85 GHz carrier frequency, while it draws 6.5 mA from a 0.6 V supply voltage. For frequency tuning, process variation, and temperature change, the amplitude change rate of the oscillation waveform in the proposed VCO is 2.1 to 3.2 times smaller than that of an existing VCO with a fixed bias. The measured amplitude change rate of the oscillation waveform for frequency tuning from 4.55 GHz to 5.04 GHz is 131 pV/Hz.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.439-442
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• 2002

We present in this Paper a microwave Power sensor fabricated by a standard CMOS process and a bulk micromachining process. The sensor consists of a CPW transmission line, a resistor as a healer, and thermocouple arrays. An input microwave heater, the resistor so that the temperature rises proportionally to the microwave power and tile thermocouple arrays convert it to an electrical signal. The sensor uses air bridged 8round of CPW realized by wire bonding to reduce tile device size and cost and to improve the thermal impedance. Al/poly-Si junctions are used for the thermocouples. Poly-Si is used for tile resister and Aluminium is for transmission line. The resistor and hot junctions of the thermocouples are placed on a low stress silicon nitride diaphragm to minimize a thermal loss. The fabricated device operates properly from 1㎼ to 100㎽\ulcorner of input power. The sensitivity was measured to be ,3.2～4.7 V/W.