• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.5
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• pp.730-736
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• 1995

This paper presents the design of a CMOS programmable slew rate operational amplifier based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. By utilizing the newly designed circuit, it was proven that slew rate was linearly controlled and power dissipation was optimized. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience of timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 5. 83V/$\mu$s to 41.4V/$\mu$s, power dissipation ranging from 1.13mW to 4.1mW, and the other circuit performance parameters were proven to be comparable with those of a conventional operational amplifier.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.11 s.353
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• pp.175-184
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• 2006

In this paper, we describe a 900MHz CMOS RF transceiver using an ISM band for ZigBee applications. The architecture of the designed rx front-end, which consists of a low noise amplifier, a down-mixer, a programmable gain amplifier and a band pass filter. And the tx front-end, which consists of a band pass filter, a programmable gain amplifier, an up-mixer and a drive amplifier. A low-if topology is adapted for transceiver architecture, and the total current consumption is reduced by using a low power topology. Entire transceiver is verified by means of post-layout simulation and is implemented in 0.18um RF CMOS technology. The fabricated chip demonstrate the measured results of -92dBm minimum rx input level and 0dBm maximum tx output level. Entire power consumption is 32mW(@1.8VDD). Die area is $2.3mm{\times}2.5mm$ including ESD protection diode pads.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1737-1741
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• 2015

A multi-channel CMOS transimpedance amplifier(TIA) array is realized in a $0.18-{\mu}m$ CMOS technology for the applications of panoramic scan LADAR systems. Each channel consists of a PIN photodiode and a feed-forward TIA that exploits an inverter input stage followed by a feed-forward common-source amplifier so as to achieve lower noise and higher gain than a conventional voltage-mode inverter TIA. Measured results demonstrate that each channel achieves $76-dB{\Omega}$ transimpedance gain, 720-MHz bandwidth, and -20.5-dBm sensitivity for $10^{-9}$ BER. Also, a single channel dissipates the power dissipation of 30 mW from a single 1.8-V supply, and shows less than -33-dB crosstalk between adjacent channels.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.129-132
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• 2000

In this paper, a 1.8㎓ low noise amplifier was designed and simulated using 0.2$\mu\textrm{m}$ Si CMOS process. Noise characteristics and s parameters were extracted for the 300$\mu\textrm{m}$ gate width and 0.25$\mu\textrm{m}$ gate length NMOS transistors. For high available power gain, each stage was designed cascode type. It revealed available power gain of 23.5dB, noise figure of 2.0dB, power consumption of 15㎽ at 2.5V. It was shown that designed low noise amplifier had good RF performance. Designed Si CMOS LNA is expected to be used for RF front-end in transceiver.

• ETRI Journal
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• v.29 no.5
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• pp.670-672
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• 2007

An ultra-wideband low-noise amplifier is proposed with operation up to 8.2 GHz. The amplifier is fabricated with a 0.18-${\mu}m$ CMOS process and adopts a two-stage cascode architecture and a simplified Chebyshev filter for high gain, wide band, input-impedance matching, and low noise. The gain of 19.2 dB and minimum noise figure of 3.3 dB are measured over 3.4 to 8.2 GHz while consuming 17.3 mW of power. The Proposed UWB LNA achieves a measured power-gain bandwidth product of 399.4 GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.232-238
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• 2008

In this paper, a wideband power efficient 2.2 GHz - 4.9 GHz Medium Power Amplifier (MPA), has been designed and fabricated using $0.8{\mu}m$ SiGe BiCMOS process technology. Passive elements such as parallel-branch spiral inductor, metal-insulator-metal (MIM) capacitor and three types of resistors are all integrated in this process. This MPA is a two stage amplifier with all matching components and bias circuits integrated on-chip. A P1dB of 17.7 dBm has been measured with a power gain of 8.7 dB at 3.4 GHz with a total current consumption of 30 mA from a 3 V supply voltage at $25^{\circ}C$. The measured 3 dB bandwidth is 2.7 GHz and the maximum Power Added Efficiency (PAE) is 41 %, which are very good results for a fully integrated Medium PA. The fabricated circuit occupies a die area of $1.7mm{\times}0.8mm$.

• Journal of electromagnetic engineering and science
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• v.17 no.1
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• pp.20-28
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• 2017

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.782-785
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• 2002

Power amplifier of wireless communication tranceiver can be effectually controlled output power. And small size and low power dissipation are indispensable to portable system. In this paper, to reduce the size of portable tranceiver, inductor is integrated in a single chip. And to reduce power dissipation, a power amplifier that can be digitally controlled output power, is proposed and designed.

• Transactions on Electrical and Electronic Materials
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• v.18 no.5
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• pp.257-260
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• 2017

In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of $703{\mu}m^2$, ensuring that the proposed circuit is suitable for low-power applications.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.309-312
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• 2002

In this paper, we discuss the design of high gain low noise amplifier by using the 0.2sum CMOS technology. A cascode inverter is adopted to implement the low noise amplifier. The proposed cascode inverter LNA is one stage amplifier with a voltage reference and without choke inductors. The designed 2.4GHz LNA achieves a power gain of 25dB, a noise figure of 2.2dB, and power consumption of 255㎽ at 2.5V power supply.