DOI QR코드

DOI QR Code

A Fully Integrated Dual-Band WLP CMOS Power Amplifier for 802.11n WLAN Applications

  • Baek, Seungjun (School of Electronic and Computer Engineering, Pusan National University) ;
  • Ahn, Hyunjin (School of Electronic and Computer Engineering, Pusan National University) ;
  • Ryu, Hyunsik (School of Electronic and Computer Engineering, Pusan National University) ;
  • Nam, Ilku (School of Electronic and Computer Engineering, Pusan National University) ;
  • An, Deokgi (RAONTECH Inc.) ;
  • Choi, Doo-Hyouk (RAONTECH Inc.) ;
  • Byun, Mun-Sub (RAONTECH Inc.) ;
  • Jeong, Minsu (RAONTECH Inc.) ;
  • Kim, Bo-Eun (RAONTECH Inc.) ;
  • Lee, Ockgoo (School of Electronic and Computer Engineering, Pusan National University)
  • Received : 2016.10.05
  • Accepted : 2016.12.30
  • Published : 2017.01.31

Abstract

A fully integrated dual-band CMOS power amplifier (PA) is developed for 802.11n WLAN applications using wafer-level package (WLP) technology. This paper presents a detailed design for the optimal impedance of dual-band PA (2 GHz/5 GHz PA) output transformers with low loss, which is provided by using 2:2 and 2:1 output transformers for the 2 GHz PA and the 5 GHz PA, respectively. In addition, several design issues in the dual-band PA design using WLP technology are addressed, and a design method is proposed. All considerations for the design of dual-band WLP PA are fully reflected in the design procedure. The 2 GHz WLP CMOS PA produces a saturated power of 26.3 dBm with a peak power-added efficiency (PAE) of 32.9%. The 5 GHz WLP CMOS PA produces a saturated power of 24.7 dBm with a PAE of 22.2%. The PA is tested using an 802.11n signal, which satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieved an EVM of -28 dB at an output power of 19.5 dBm with a PAE of 13.1% at 2.45 GHz and an EVM of -28 dB at an output power of 18.1 dBm with a PAE of 8.9% at 5.8 GHz.

Keywords

References

  1. S. C. Cripps, RF Power Amplifiers for Wireless Communication. Boston, MA: Artech House, 1999, pp. 246-248.
  2. X. Fan and Q. Han, "Reliability challenges and design considerations for wafer-level packages," in Proceedings of International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), Shanghai, China, 2008, pp. 1-6.
  3. J. J. Reche and D. H. Kim, "Wafer level packaging having bump-on-polymer structure," Microelectronics Reliability, vol. 43, no. 6, pp. 879-894, 2003. https://doi.org/10.1016/S0026-2714(03)00058-1
  4. B. Rogers, C. Scanlan, and T. Olson, "Implementation of a fully molded fan-out packaging technology," in Proceedings of 10th International Wafer-Level Packaging Conference (IWLPC), San Jose, CA, 2013, pp. 1-6.
  5. R. Kumar, T. Krishnaswamy, G. Rajendran, D. Sahu, A. Sivadas, M. Nandigam, et al, "A fully integrated 2 $\times$ 2 b/g and 1 $\times$ 2 a-band MIMO WLAN SoC in 45nm CMOS for multi-radio IC," in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, 2013, pp. 328-329.
  6. O. El-Gharniti, E. Kerherve, and J. B. Begueret, "Modeling and characterization of on-chip transformers for silicon RFIC," IEEE Transactions on Microwave Theory and Techniques, vol. 55, no. 4, pp. 607-615, 2007. https://doi.org/10.1109/TMTT.2007.893647
  7. M. Albulet, RF Power Amplifiers. Atlanta, GA: Noble Publishing, 2001, pp. 9-41.
  8. O. Lee, H. Ryu, S. Baek, I. Nam, M. Jeong, and B. E. Kim, "A high-efficiency CMOS power amplifier using 2:2 output transformer for 802.11n WLAN applications," Journal of Semiconductor Technology and Science, vol. 15, no. 2, pp. 280-285, 2015. https://doi.org/10.5573/JSTS.2015.15.2.280
  9. S. Baek, H. Ryu, I. Nam, M. Jeong, B. E. Kim and O. Lee, "A 2.4-GHz CMOS power amplifier with parallel-combined transistors and selective adaptive biasing for wireless LAN applications," Microwave and Optical Technology Letters, vol. 58, no. 6, pp. 1374-1377, 2016. https://doi.org/10.1002/mop.29810
  10. T. M. Chen, W. C. Chan, C. C. Lin, J. L. Hsu, W. K. Li, P. A. Wu, et al, "A 2 $\times$ 2 MIMO 802.11 abgn/ac WLAN SoC with integrated T/R switch and on-chip PA delivering VHT80 256QAM 17.5 dBm in 55nm CMOS," in Proceedings of 2014 IEEE Radio Frequency Integrated Circuits Symposium, Tampa Bay, FL, 2014, pp. 225-228.
  11. D. Guo, "Power amplifier and front end module requirements for IEEE 802.11n applications," High Frequency Electronics, vol. 10, no. 9, pp. 38-45, 2011.

Cited by

  1. A 5.5-GHz CMOS power amplifier using parallel-combined transistors with cascode adaptive biasing for WLAN applications vol.15, pp.9, 2018, https://doi.org/10.1587/elex.15.20180336
  2. Design of Experiment (DOE) Analysis of System Level ESD Noise Coupling to High-Speed Memory Modules vol.8, pp.2, 2019, https://doi.org/10.3390/electronics8020210