• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.2
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• pp.138-143
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• 2003

A double spiral thin-film inductor with a NiFe magnetic core is integrated with DC-DC converter IC. The NiFe core is deposited on a polyimide film as the thinckness of NiFe is 2.5~3.5 ${\mu}$m. Then, copper conductor line is deposited on the NiFe core with double spiral structure. Process integration is performed by sequential processes of etching the polyimide film deposited both top and bottom of the NiFe core and electroplation copper conductor line from exposed metal pad of the DC-DC converter IC. Process integration is simplified by elimination planarization process for top core because the proposed thin-film inductor has a bottom NiFe core only. Inductor of the fabricated monolithic DC-DC converter IC is 0.53 ${\mu}$H when the area of converter IC and thin-film inductor are 5X5$\textrm{mm}^2$ and 3.5X2.5$\textrm{mm}^2$, respectively. The efficiency is 72% when input voltage and output voltage are 3.5 V and 6 V, respectively at the operation frequency of 8 MHz.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.104-107
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• 2000

We designed and implemented the RFIC(RF front-end IC) for DTV(Digital TV) tuner. The DTV tuner RF front-end consists of low noise IF amplifier fur the amplification of 900 MHz RF signal and down conversion mixer for the RF signal to 44MHz IF conversion. The RFIC is implemented on ETRI 0.8u high resistive (2㎘ -cm) and evaluated by on wafer, packaged chip test. The gain and IIP3 of IF amplifier are 15㏈ and -6.6㏈m respectively. For the down conversion mixer gain and IIP3 are 13㏈ and -6.5㏈m. Operating voltage of the IF amplifier and the down mixer is 5V, current consumption are 13㎃ and 26㎃ respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.6
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• pp.637-646
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• 1988

The CMOS physical parameters are extracted using by processing models in fabrication steps, processing parameters, fabrication disturbances, control parameters. Statistical CMOS process and device simulator is proposed to evaluate the effect of inherent fluctuations in IC fabrication. Using this simulator, we perform worst case analysis in terms of statistically independent disturbances and compare this proposed method to Monte Carlo method, previous Worst Case method. And simulation results with this proposed method are more accurate than the past worst case analysis. This package is written in C language and runs on a IBM PC AT(OPUS).

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.8
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• pp.172-180
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• 1994

Implantable biotelemetry systems are indispensable tools not only in animal research but also in clinical medicine as such systems enable the acquisition of otherwise unavailable physiological data. We present the manufacture of CMOS IC and its system for implantable multichannel biotelemeter system. The internal circuits of this system are designed not only to achieve as multiple functions and low power dissipation as possible but also to enable continuous measurement of physiological data. Its main functions are to enable continuous measurement of physiological data and to accomplish on-off power swiching of an implantable battery by receiving appropriate commanc signals from an external circuit. The implantable circuits of this system are designed and fabricated on a single silicon chip using $1.5\mu$m n-well CMOS process technology. The total power dissipation of implantable circuits for a continuous operation was 6.7mW and for a stand-by operation was 15.2$\mu$ W. This system used together with approriate sensors is expected to contribute to clinical medicine telemetry system of measuring and wireless transmitting such significant physiological parameters as pressure pH and temperature.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.389-392
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• 1999

It is essential to estimate an effective inductance in a ground plane of muliti-layer IC package system in order to determine the simultaneous switching noise of the package. A new method to estimate the effective ground inductance in multi-layer IC package is presented. With the estimated ground plane inductance values, maximum switching noise variations according to the number of simultaneously switching drivers are investigated by developing a new SSN model. These results are verified by performing HSPICE simulation with the 0.35${\mu}{\textrm}{m}$ CMOS technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.474-480
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• 2003

We designed and tested a new scan driver output stage. Compared to conventional CMOS structured scan driver IC′s, the new NMOSFET-only scan driver circuit can reduce the chip area and therefore, the chip cost considerably. We confirmed the circuit operation with open drain power NMOSFET IC′s by driving 2"PDP test panel. We defined critical device parameters and their optimization methods lot the best circuit performance.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.164-165
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• 2007

파워 IC 공정은 CMOS 공정과 달리 내압별로 다양한 소자가 제공되며 BJT와 DMOS 구조를 포함할 경우 매스크가 20장이 넘는 매우 복잡한 공정이다. 본 논문에서는 국내의 파운드리 기업인 동부하이텍과 매그나칩사에서 제공하는 파워 IC 공정 및 제공되는 소자의 특성을 비교 분석하였다.

• Journal of Korea Society of Industrial Information Systems
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• v.12 no.2
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• pp.79-84
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• 2007

This papar reports design and fabrication of CMOS temperature control circuit using MOSIS 0.25um-3.3V CMOS technology. The proposed circuit has a temperature coefficient of $13mV/^{\circ}C$ for a wide operating temperature range with a good linearity. Furthermore, the temperature coefficient of output voltage can be controlled by adjusting external bias voltage. This circuit my be applicable to the design of one-chip IC where quartz crystal resonator is mounted on CMOS oscillator chips.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.9
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• pp.535-540
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• 2017

The changes in the electrical characteristics of CMOS ICs due to coupling with a narrow-band electromagnetic wave were analyzed in this study. A magnetron (3 kW, 2.45 GHz) was used as the narrow-band electromagnetic source. The DUT was a CMOS logic IC and the gate output was in the ON state. The malfunction of the ICs was confirmed by monitoring the variation of the gate output voltage. It was observed that malfunction (self-reset) and destruction of the ICs occurred as the electric field increased. To confirm the variation of electrical characteristics of the ICs due to the narrow-band electromagnetic wave, the pin-to-pin resistances (Vcc-GND, Vcc-Input1, Input1-GND) and input capacitance of the ICs were measured. The pin-to-pin resistances and input capacitance of the ICs before exposure to the narrow-band electromagnetic waves were $8.57M{\Omega}$ (Vcc-GND), $14.14M{\Omega}$ (Vcc-Input1), $18.24M{\Omega}$ (Input1-GND), and 5 pF (input capacitance). The ICs exposed to narrow-band electromagnetic waves showed mostly similar values, but some error values were observed, such as $2.5{\Omega}$, $50M{\Omega}$, or 71 pF. This is attributed to the breakdown of the pn junction when latch-up in CMOS occurred. In order to confirm surface damage of the ICs, the epoxy molding compound was removed and then studied with an optical microscope. In general, there was severe deterioration in the PCB trace. It is considered that the current density of the trace increased due to the electromagnetic wave, resulting in the deterioration of the trace. The results of this study can be applied as basic data for the analysis of the effect of narrow-band high-power electromagnetic waves on ICs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.1-10
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• 2006

In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.