• IEIE Transactions on Smart Processing and Computing
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• v.5 no.3
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• pp.207-214
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• 2016

Optical communication systems are rapidly spread following increases in data traffic. In this work, a 32-Gb/s inductorless output buffer circuit with adjustable pre-emphasis is proposed. The proposed circuit consists of an output buffer circuit and an emphasis circuit. The emphasis circuit emphasizes the high frequency components and adds the characteristics of the output buffer circuit. We proposed a design method using a small-signal equivalent-circuit model and designed the compensation characteristics with a 65-nm CMOS process in detail using HSPICE simulation. We also realized adjustable emphasis characteristics by controlling the voltage. To confirm the advantages of the proposed circuit and the design method, we fabricated an output buffer IC with adjustable pre-emphasis. We measured the jitter and eye height with a 32-Gb/s input using the IC. Measurement results of double-emphasis showed that the jitter was 14% lower, and the eye height was 59% larger than single-emphasis, indicating that our proposed configuration can be applied to the design of an output buffer circuit for higher operation speed.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.6
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• pp.2707-2712
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• 2011

In this paper, a power factor correction (PFC) control circuit using single stage boundary conduction mode(BCM) for the 400V. 120W LED drive application has been designed. The proposed control circuit is aimed for improvement of the power factor correction and reduction of the total harmonic distortion. In this circuit, a new CMOS multiplier structure is used instead of a conventional BJT(bipolar junction transistor) based multiplier where has a relatively large area. The CMOS multiplier can bring 30 % reduced chip area, competitive die cost in comparison with the conventional BJT multiplier.

• Journal of IKEEE
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• v.15 no.3
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• pp.205-210
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• 2011

A novel hysteresis tunable monolithic comparator circuit based on a 0.35 ${\mu}m$ CMOS process is suggested in this paper. To tune the threshold voltage of the hysteresis in the comparator circuit, two external digital bits are used with supply voltage of 3.3V. The threshold voltage of the suggested comparator circuit is controlled by 234mV by change of 4 digital control bits in the simulation, which is a close agreement to the analytic calculation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.4
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• pp.367-370
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• 2004

We fabricated SiGe BiCMOS devices, which are important for ultra high speed RF IC chips, by employing $0.35\mu{m}$ CMOS process. To meet with the requirement of low noise level with linear base leakage current at low VBE region, we try to minimize polysilicon/ silicon interface traps by optimizing capping silicon thickness and EDR(emitter drive-in RTA) temperature. We employed $200\AA$and $300\AA$-thick capping silicon, and varied the EDR process condition at temperature of $900-1000^\circ{C}$, and time of 0-30 sec at a given capping silicon thickness. We investigated current gain behavior at each process condition. We suggest that optimum EDR process condition would be $975^\circ{C}$-30 sec with $300\AA$-thick capping silicon for proposed $0.35\mu{m}$-SiGe HBT devices.

• ETRI Journal
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• v.32 no.2
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• pp.327-329
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• 2010

A fully integrated small form-factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix-on-pad integrated passive device output matching, a chip-stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm ${\times}$ 2.2 mm. A stage-bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.909-912
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• 2005

According to miniaturization trend of rehabilitation medical equipment such as hearing aid, study to replace previous complex system with semiconductor SOC (System-on-Chip) chip becomes lively. In this study, after investigating of existent hearing aid performance in circuit design approach, low electric power consuming, single power supply (1.4V battery) CMOSS OP AMP was designed. Analog circuit design tools such as Hspice and Cadence were used for circuit simulation and implementing layout design. This study shows technical methods particularly for layout design. The work is done in pmos and nmos active element layout design in addition to passive element design such as resister, capacitor and inductor.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.7
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• pp.58-68
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• 1995

Polysilicon capacitors with pyrogenic oxide and TEOX oxide as insulators were fabricated to develop capacitors which can be applied to analog CMOS IC, and the characteristics of the capacitors were compared with each other. The morphology of bottom polysilicon in pyrogenic oxide capacitor is degraded due to the generaged protuberances of the polysilicon grain during oxidataion. The polysilican capacitor with pyrogenic oxide of 57 nm thickness showed that the effective potential barrier height of 0.45 eV is much less than that of MOS capacitor (3.2 eV)when the top electrode is biased with a positive volgate. The morphology of the polysilicon capacitor with TEOS oxide, however, was not degraded during oxide deposition by LPCVD. The polysilicon capacitor with TEOS oxide of 54 nm thickness showed the effective potential barrier height of 1.28 eV when the top electrode is biased with a negative voltage. Therefore, it is concluded that the polysilicon capacitor with TEOS oxide is more applicable to analog CMOS IC than the pyrogenic oxide polysilicon capacitor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• Journal of Sensor Science and Technology
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• v.6 no.3
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• pp.194-199
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• 1997

When voltage or current gets out of the magnetic sensor as it is, we have often faced the problems such as introduction of noise and loss of voltage. In order to reduce these problems, a 2 drain MAGFET operating in the saturation region and fabricated by CMOS process, the system of I/V converter, VCO with operational amplifier, and V/F conversion circuits with Schmitt Trigger are designed and fabricated in one package. The absolute sensitivity of magnetic sensor shows 1.9 V/T and the product sensitivity is $3.2{\times}10^{4}\;V/A{\cdot}T$. The characteristic of V/F conversion is very stabilized and has the value of 190 kHz/T.