• Journal of Advanced Navigation Technology
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• v.7 no.2
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• pp.206-210
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• 2003

In this paper, we design standard cell libraries using the 0.18um deep submircom CMOS process, and port them into a P&R (Placement and Routing) CAD tool. A simple test chip has been designed in order to verify the functionalities of the 0.18um standard cell libraries whose technical process was provided by Anam semiconductor. Through these experiments, we have found that the new 0.18um CMOS process can be successfully applied to automatic digital system design.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2005.05a
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• pp.914-921
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• 2005

신제품으로 개발 중인 초소형 CMOS RF 전압 제어발진기(VCO) IC 에 대한 공인된 시험 규격은 현재 개발되어 있지 않다. 또한 제조업체들은 고유의 시험방법을 보유하고 있을 것이나 공개하지 않고 있는 실정이다. 한편 일부 해외 제조업체에서 국제 규격인 IEC 또는 JEDEC 을 기준으로 시험방법을 제시하고 있지만, 이러한 시험규격들은 개별 부품을 솔더링하는 하이브리드 공정을 이용하여 제작된 VCO 를 대상으로 한 것이다. 그러므로 CMOS 반도체 공정을 이용한 IC 형으로 개발 중인 VCO 를 평가하기에는 적합하지 않다. 이에 본 연구에서는 신개발 부품인 CMOS RF VCO IC 에 대한 신뢰성 시험 및 평가 기준을 수립하고, 신뢰성 확보를 위한 신제품 개발 단계에서의 신뢰성 평가 프로세스를 개발하고자 한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.771-773
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• 2014

본 논문에서는 장거리 레이더용 차량 충돌 방지 77-GHz CMOS 믹서를 제안한다. 이러한 회로는 2볼트 전원전압에서 동작하며, 저 전압 전원 공급에서도 높은 변환 이득과 낮은 변환 손실 및 낮은 잡음지수를 가지도록 설계되어 있다. 제안한 회로는 TSMC $0.13{\mu}m$ 혼성신호/고주파 CMOS 공정($f_T/f_{MAX}=120/140GHz$)으로 설계하였다. 전체 칩 면적을 줄이기 위해 수동형 인덕터 대신 전송선(Transmission Line) 을 이용하였다. 본 논문에서 설계한 믹서는 약 5.2dB의 우수한 변환이득 특성과 2.1dBm의 우수한 IIP3 특성을 보였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.131-136
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• 2008

Two Ka-band 3-stage power amplifiers were designed and fabricated using $0.18-{\mu}m$ CMOS technology. For low loss matching networks for the amplifiers, two substrate-shielded transmission line structures, having good modeling accuracy up to 40 GHz were used. The measured insertion loss of substrate-shielded microstrip-line (MSL) was 0.5 dB/mm at 27 GHz. A 3-stage CMOS amplifier using substrate-shielded MSL achieved a 14.7-dB small-signal gain and a 14.5-dBm output power at 27 GHz in a compact chip area of 0.83$mm^2$. The measured insertion loss of substrate-shielded coplanar waveguide (CPW) was 1.0 dB/mm at 27 GHz. A 3-stage amplifier using substrate-shielded CPW achieved a 12-dB small-signal gai and a 12.5-dBm output power at 26.5 GHz. This results shows a potential of CMOS technology for low cost short-range wireless communication components and system.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.9
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• pp.54-61
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• 1998

A new Triple well structure is proposed for improved latch-up immunity at deep submicron CMOS device. Optimum latch-up immunity process condition is established and analyzed with varying ion implantation energy and amount of dose and also compared conventional twin well structure. Doping profile and structure are investigated using ATHENA which is process simulator, and then latch-up current is calculated using ATLAS which is device simulator. Two types of different process are affected by latch-up characteristics and shape of doping profiles. Finally, we obtained the best latch-up immunity with 2.5[mA/${\mu}{m}$] trigger current using 2.5 MeV implantation energy and 1$\times$10$^{14}$ [cm$^{-2}$ ] dose at p-well

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.6
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• pp.141-147
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• 2008

This paper describes the design of frequency down converting Mixer in the receiver to use compound semiconductor and CMOS product process. The basic theory and structure of frequency down converting Mixer is surveyed, and we design mixer circuit with active balun which use the compound semiconductor and CMOS process. This mixer convert a single ended signal to differential signal at input port of RF and LO instead of matching circuit to get dual band balanced mixer structure and characteristic broadband. This designed mixer has a conversion gain $-1{\sim}-6[dB]$ at $2{\sim}6[GHz]$ bandwidths. However, the simulation of the designed mixer with active balun has the result of a 7[dB] conversion gain for -2[dBm] LO input power and -10[dBm] input P1[dB] at 5.8[GHz].

• Review of KIISC
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• v.2 no.2
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• pp.64-80
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• 1992

전화망을 통과하는 음성신호에 대하여, 실시간에 공개열쇠방식의 암호화/복호화를 하기 위한 반도체 IC제조공정평가를 실시하였다. 초당 64k bit의 정보에 대하여 256 bit이상의 key를 갖는 RSA 방식 암호화를 위하여 modular multiplication 환경과 redundant number system을 채택하여 algori-multiple input shift register 를 사용하는 회로로 충족시키는 과정에서, 1.0 $이하의 CMOS공정이 요구된다는 결론에 도달하였으며, 이들 회로의 타당성은 저속 RSA chip의 분석 결과와 비교하여 확인하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.3
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• pp.278-285
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• 2013

In this paper, a 100~110 GHz LNA and A coupler using standard 65 n CMOS process is presented. The LNA consists of three common source FET stages. A few layout types are considered to get high gain characteristic of unit common source cell. Also, optimized performance to achieve low noise characteristic and enough gain. Coupler is composed of broadside coupler using multimetal in CMOS fabrication. In the coupler, the metal strip to meet density rule is used, and the coupler is designed with consideration of the metal strip to function properly. Gain of fabricated LNA is 5.64 dB at 100 GHz and 6.39 dB at 110 GHz. Bandwidth is over 10 % and noise figure is 11.66 dB at 100 GHz. Fabricated coupler has shown insertion loss of 2~3 dB at 100~110 GHz band. Magnitude mismatch of coupler is below 1 dB and phase mismatch of coupler is below $5^{\circ}$.

• Journal of IKEEE
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• v.9 no.1 s.16
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• pp.57-64
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• 2005

This paper presents a built-in current sensor(BICS) that detects defects in CMOS integrated circuits using the current testing technique. This circuit employs a cross-coupled connected PMOS transistors, it is used as a current comparator. The proposed circuit has a negligible impact on the performance of the circuit under test (CUT) and high speed detection time. In addition, in the operation of the normal mode, the BlCS does not have dissipation of extra power, and it can be applied to the deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The area overhead of a BlCS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS standard technology.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.399-401
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• 2008