• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.1-9
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• 2003

In this paper, a novel Ni silicide technology with Cobalt interlayer and Titanium Nitride(TiN) capping layer for sub 100 nm CMOS technologies is presented, and the device parameters are characterized. The thermal stability of hi silicide is improved a lot by applying co-interlayer at Ni/Si interface. TiN capping layer is also applied to prevent the abnormal oxidation of NiSi and to provide a smooth silicidc interface. The proposed NiSi structure showed almost same electrical properties such as little variation of sheet resistance, leakage current and drive current even after the post silicidation furnace annealing at $700^{\circ}C$ for 30 min. Therefore, it is confirmed that high thermal robust Ni silicide for the nano CMOS device is achieved by newly proposed Co/Ni/TiN structure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.31-39
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• 2009

This paper presents the single supply power line communication(PLC) SoC ASIC with built-in analog frond-end circuit. To achieve the low power consumption along with low chip cost, this PLC SoC ASIC employs fully CMOS analog front-end(AFE) and several built-in Regulators(LDOs) powering for Core logic, ADC, DAC and IP Pad driver. The AFE includes RX of pre-amplifier, Programmable gain amplifier and 10 bit ADC and TX of 10bit Digital Analog Converter and Line driver. This PLC Soc was implemented with 0.18um 1 Poly 5 Metal CMOS process. The single power supply of 3.3V is required for the internal LDOs. The total power consumption is below 30mA at standby and 300mA at active which meets the eco-design requirement. The chips size is $3.686\;{\times}\;2.633\;mm^2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.04b
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• pp.68-71
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• 2004

본 연구는 싱크로트론 방사광의 단색광 (monobeam)을 이용한 영상을 획득하였다. 영상센서로서 CMOS를 사용하였으며 센서 앞단에는 형광체 (phosphor)를 이용하여 방사광에 대한 빛의 신호로서 영상을 획득하였다. 사용된 싱크로트론 방사광의 beam size는 $5mm{\times}2mm$ 이며 ion chamber를 통한 beam intensity 는 $10{\times}10^{-7}$이다. 형광체는 각각 ZnS(Cu:Al), ZnS(Ag,Al), $BiTiO_3$, $Y_2O_2S(Tb)$로서 4가지를 사용하였으며 여기에 사용된 형광체는 기계식 스크린 프린팅 (Screen Printing) 방식으로 직접 제조하였다. 두께는 모두 동일하게 $10{\mu}m$이며 각각에 대한 PL(Photoluminescence)을 측정하여 분석하였다. object로는 물고기와 20linepair를 사용하였으며 CMOS센서를 이용하여 각각의 phosphor에 대하여 영상을 획득하였다. 영상의 평가는 20line pair 영상의 MTF를 이용하였다. 각각의 형광체에 대한 MTF는 5 lp/mm 에서는 0.5650, 0.2150, 0.7890, 0.3840 이며 10 lp/mm 은 0.4500, 0.0900, 0.2510, 0.1500이고 15 lp/mm 는 0.1900, 0.0300, 0.1430, 0.0500이며 마지막으로 20 lp/mm 은 0.0810, 0.004, 0.0500, 0.0320의 MTF 값을 나타내었다. $10{\mu}m$ 두께에 대하여 ZnS(Cu:Al)이 가장 좋은 MTF의 값을 나타내었다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8B
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• pp.787-795
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• 2002

This paper presents the architecture and the implementation of a 2K/4K/8K-point complex Fast Fourier Transform(FFT) processor for Orthogonal Frequency-Division Multiplexing (OFDM) system. The architecture is based on the Cooley-Tukey algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition memory, shuffle memory, and memory mergence method are used for the efficient manipulation of data for multi-dimensional transforms. Booth algorithm and the COordinate Rotation DIgital Computer(CORDIC) processor are employed for the twiddle factor multiplications in each dimension. Also, for the CORDIC processor, a new twiddle factor generation method is proposed to obviate the ROM required for storing the twiddle factors. The overall 2K/4K/8K-FFT processor requires 600,000 gates, and it is implemented in 1.8 V, 0.18 ${\mu}m$ CMOS. The processor can perform 8K-point FFT in every 273 ${\mu}s$, 2K-point every 68.26 ${\mu}s$ at 30MHz, and the SNR is over 48dB, which are enough performances for the OFDM in DVB-T.

• Toxicological Research
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• v.27 no.2
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• pp.125-131
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• 2011

Through the present study, we produced a monoclonal antibody against aflatoxin B1 (AFB1) using AFB1-carboxymethoxylamine BSA conjugates. One clone showing high binding ability was selected and it was applied to develop a direct competitive ELISA system. The epitope densities of AFB1-CMO against BSA and KLH were about 1 : 6 and 1 : 545, respectively. The monoclonal antibody (mAb) from cloned hybridoma cell was the IgG1 subclass with ${\lambda}$-type light chains. The $IC_{50}s$ of the monoclonal antibody developed for AFB1, AFB2, AFG1 and AFG2 were 4.36, 7.22, 6.61 and 29.41 ng/ml, respectively, based on the AFB1-KLH coated ELISA system and 15.28, 26.62, 32.75 and 56.67 ng/ml, respectively, based on the mAb coated ELISA. Cross-relativities of mAb to AFB1 for AFB2, AFG1 and AFG2 were 60.47, 65.97 and 14.83% in the AFB1-KLH coated ELISA, and 59.41, 46.66 and 26.97% in the mAb coated ELISA, respectively. Quantitative calculations for AFB1 from the AFB1-Ab ELISA and AFB1-Ag ELISA ranged from 0.25 to 25 ng/ml ($R^2$ > 0.99) and from 1 to 100 ng/ml ($R^2$ > 0.99), respectively. The intra- and inter-assay precision CVs were < 10% in both ELISA assay, representing good reproducibility of developed assay. Recoveries ranged from 79.18 to 91.27%, CVs ranged from 3.21 to 7.97% after spiking AFB1 at concentrations ranging from 5 to 50 ng/ml and following by extraction with 70% methanol solution in the Ab-coated ELISA. In conclusion, we produced a group specific mAb against aflatoxins and developed two direct competitive ELISAs for the detection of AFB1 in feeds based on a monoclonal antibody developed.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.152-152
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• 2011

Silicon 기반의 환경에서 연구 및 제조되는 전자소자는 반도체의 기술이 발전함에 따라 chip 선폭의 크기가 30 nm에서 20 nm, 그리고 그 이하의 크기로 점점 더 작아지는 요구에 직면하고 있다. 탄소나노 구조와 나노와이어 기술이 Silicon을 대신할 다음세대 기술로 주목받고 있다. 많은 연구결과들 중에서 III-V CMOS가 가장 빠른 접근 방법이라 예상한다. III-V족 물질을 이용하면 electron 보다 수십 배 이상의 이동도를 얻을 수 있으나 p-type의 구조를 구현하는 것이 해결해야 할 문제이다. p-type 3-5 족 화합물을 이용하여 에너지 밴드 갭의 변화를 가능하게 한다면 hole의 이동도를 크게 향상시킬 수 있어 silicon 기반의 p-type 소자보다 2~3배 더 빠른 소자의 구현이 가능하다. 3-5족 화합물 반도체의 성장 기술이 많이 진보되어 이를 이용하여 고속 소자를 구현한다면 시기적으로 더욱 빨리 다가올 것이라 예측한다. 에너지 밴드갭의 변화와 격자 부정합을 고려하여 SI InP 기판에 GaSb 물질을 채널로 사용한 p-type 2-dimensional hole gas (2DHG) 소자를 구현하였다. 관찰된 소자 구조의 박막 상태의 특징을 보이며 10 um ${\times}$ 10 um AFM 측정결과 1 nm 이하의 표면 거칠기를 가지며 상온에서의 hole 이동도는 약 650 cm2/Vs이고 sheet carrier density는 $5{\times}1012$ /cm2의 결과를 확인하였다. 실험결과 InP 기판위에 채널로 사용된 GaSb 박막을 올리는데 있어 가장 중요한 것은 Phosphorus, Arsenic, 그리고 Antimony 물질의 양과 이들의 변화시간의 조절이다. 본 발표에서 Semi-insulating InP 기판위에 electron이 아닌 hole을 반송자로 이용한 차세대 고속 전자소자를 구현하고자 하여 MBE (Molecular Beam Epitaxy)로 p-type 소자를 구현하여 실험하였다. 아울러 더욱 빠른 소자의 구현을 위하여 세계의 유수 그룹들의 연구 결과들과 앞으로 예상되는 고속 소자에 대해서 비교와 함께 많은 기술에 대해 논의하고자 한다.

• The Journal of the Korea Contents Association
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• v.11 no.5
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• pp.205-215
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• 2011

Films are sensitive to ultraviolet rays and in contrast, digital camera sensors are extremely sensitive to infrared rays due to the differences in spectral characteristics. As a result, all digital cameras that use CCD or CMOS are equipped with IR Cut-Off Filter on the overall sensor. Complete block out of infrared rays is ideal, but the actual experiment results showed that infrared rays were not being blocked out completely. Infrared permeability was also different for each camera. Therefore, this study aims to analyze the effect of the minute quantities of infrared rays, which get transmitted due to mechanical properties of IR Cut-Off Filters that are installed on digital cameras, on digital picture images. The results obtained by carrying out a comparative analysis of a UV Filter (infrared transmitting state) and a UV-IR Filter (infrared blocked out state) are as follows. It was confirmed that the minute quantities of infrared rays do affect dynamic range and resolution to some extent, despite the little or no difference in noise and color reproduction.

• Korean Journal of Optics and Photonics
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• v.8 no.6
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• pp.500-505
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• 1997

Experimental amorphous photodiode is fabricated on CMOS IC using a-Si:H p-i-n structure. Amorphous photodiode is scuccessfully integrated on CMOS IC using amorphous Si produced by PECVD system. The PECVD system can deposit a-Si:H at low temperature so that photodiode can be integrated with CMOS IC structure without any process incompatibility. The fabricated amorphous photodiode has a breakdown voltage of below -20 V, a leakage current of about 1 $\mu\textrm{A}$, and turn-on voltage of 0.6~0.8 V. It is demonstrated that the photocurrent of optical signal can be turned on and off by a small voltage and the fabricated amorphous p-i-n photodiode can be used as an optical switch.

• Korean Journal of Optics and Photonics
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• v.23 no.3
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• pp.97-102
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• 2012

In general, one of the methods used to measure distortion is to use the full image of the regular pattern. However, because of low accuracy, this method is mainly used for an optical system such as a camera.. In order to measure distortion with high accuracy less than 1um, one can use the method of measuring the exact position of a mask image. In this case, a high accuracy stage with a laser encoder is required. In this paper, we investigate measurement of the distortion of high accuracy with a simple manual stage. The main idea is that we split and measure the mask image with the overlapping area by using CCD or CMOS, and then we get an exact position of the mask image by integrating the adjacent split images. We use the Canny Edge Detection method to get the position information of the mask image and we researched the process to exactly calculate distortion by using coordinate transformations and a least square method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.77-83
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• 2004

In low-power VLSI systems, it is effective to suppress leakage current by shutting down megablocks in idle states. Recently, multi-threshold voltage CMOS (MTCMOS) is widely accepted to shutdown power supply. However, it requires short wake-up time as operating frequency increases. This causes large current surge during wake-up process, and it often leads to system malfunction due to severe Power line noise. In this paper, a novel wake-up scheme is proposed to solve this problem. It exploits pipelined wake-up strategy in several stages that reduces maximum current on the power line and its corresponding power line noise. To evaluate its efficiency, the proposed scheme was applied to a multiplier block in the Compact Flash memory controller chip. Power line noise in shutdown and wake-up process was simulated and analyzed. From the simulation results, the proposed scheme was proven to greatly reduce the power line noise compared with conventional schemes.