• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.8A
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• pp.644-649
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• 2003

Novel 622Mb/s burst-mode clock and data recovery (CDR) circuits with muxed oscillators are realized for passive optical network (PON) application. The CDR circuits are implemented with 0.35$\mu\textrm{m}$ CMOS process technology. Lock is accomplished on the first data transition and data are sampled in the optimal point. The experimental results show that the proposed CDR circuits recover the incoming 400Mbps-680Mbps burst mode input data without error.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.455-458
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• 2011

4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard $0.18{\mu}m$ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation.

• Journal of Electrical Engineering and Technology
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• v.2 no.1
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• pp.81-88
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• 2007

This paper proposes a coupled inductor-based rectifier of a Three-Level (TL) DC/DC converter and compares the rectification methods of a TL converter. The CICDR- TL (Coupled Inductor Current Doubler Rectifier Three-Level) converter achieves ZVS (Zero Voltage Switching) for the switches in a wide load range. CDR (Current Doubler Rectifier) and CICDR Three-Level converter have low voltage and current ripple. Advantages and disadvantages of topology compared to the rectifier of bridge, center-tap, CDR, and CICDR are discussed. Experimental estimation results are obtained on a 27V, 60A DC/DC TL converter prototype for the 1.8kW, 40kHz IGBT based experimental circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2B
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• pp.69-75
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• 2008

We propose new routing scheme, Cooperative Diversity-based Routing (CDR)which utilize the cooperative space diversity for power saving and for performance enhancement of wireless ad-hoc networks. The end-to-end performance of the proposed routing, CDR, is analyzed based on the Haenggi's link model. The improved performance is compared with Multi-hop Relay Routing (MRR) by analytical methods. When the required outage probability is $1{\times}10^{-3}$ at the destination node in ad-hoc networks with 7 nodes, we noticed that each node can save power consumption by 21.5 dB in average, by using our proposed CDR compared to MRR.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.71.2-71.2
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• 2013

천연가스를 화학적 전환에 의해 부가가치를 높이기 위해서는 리포밍에 의해 합성가스(CO/H2)를 경유하는 간접전환경로가 현재로서는 가장 현실적인 방법이라 할 수 있다. 천연가스를 이용한 합성가스 제조기술은 수증기개질법(SRM), 이산화탄소 개질법(CDR, dry reforming), 부분산화법, 촉매 부분 산화법, 자열개질법 등으로 구분되며, 최근에는 각각의 제조방법의 장점을 고려하여 혼합개질법 또는 일련의 리포머 조합 방법이 개발되고 있다. CDR은 촉매 하에서 메탄과 이산화탄소의 직접접촉에 의해 반응이 일어나며, 수소와 일산화탄소의 비가 같은 합성가스가 제조된다. SRM에 비하여 고온에서 반응이 일어나고 전환율이 더 낮으므로 에너지 소비가 상대적으로 높다. 하지만, SRM과 함께 사용하면 합성가스 비율을 F-T합성이나 메탄올 합성에 적절한 비율로 조절이 가능한 장점이 있으며, 온실가스를 저감시킬 수 있는 전환기술로도 각광받고 있다. 본 발표에서는 최근의 CDR을 이용한 가스로부터 합성석유(GTL)와 메탄올을 고효율로 생산하는 기술 개발 동향에 대해서 소개하고자 한다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.7-13
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• 2009

This paper presents a multi-channel transceiver that achieves a data rate of 3.125Gb/s/ch. The LVDS is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. On the receiver side, a low-power CDR(clock and data recovery) using 1/4-rate clock based on dual-interpolator is proposed. The CDR generates needed additional clocks in each recovery part internally using only inverters. Therefore each part can be supplied with the same number of 1/4-rate clocks from a clock generator as in 1/2-rate clock method. Thus, the reduction of a clock frequency relaxes the speed limitation and lowers power dissipation. The prototype chip is comprised of two channels and was fabricated in a $0.18{\mu}m$ standard CMOS process. The output jitter of transmitter is loops, peak-to-peak(0.31UI) and the measured recovered clock jitter is 47.33ps, peak-to-peak which is equivalent to 3.7% of a clock period. The area of the chip is $3.5mm^2$ and the power consumption is about 119mW/ch.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.87-95
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• 2013

In this paper, 2.5 Gb/s burst-mode clock and data recovery(CDR) is presented. Digital frequency calibration scheme is adopted to eliminate mismatch between the input data rate and the output frequency of the gated voltage controlled oscillator(GVCO) in the clock recovery circuitry. A jitter rejection scheme is also used to reduce jitter caused by input data. The proposed burst-mode CDR is designed using 0.11 ${\mu}m$ CMOS technology. Post-layout simulations show that peak-to-peak jitter of the recovered data is 14 ps with 0.1 UI input referred jitter, and maximum tolerance of consecutive identical digit(CID) is 2976 bits without input data jitter. The active area occupies 0.125 $mm^2$ without loop filter and the total power consumption is 94.5 mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of Platform Technology
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• v.9 no.3
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• pp.3-17
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• 2021

Advanced persistent threat (APT) attacks are attacks aimed at a particular entity as a set of latent and persistent computer hacking processes. These APT attacks are usually carried out through various methods, including spam mail and disguised banner advertising. The same name is also used for files, since most of them are distributed via spam mail disguised as invoices, shipment documents, and purchase orders. In addition, such Infostealer attacks were the most frequently discovered malicious code in the first week of February 2021. CDR is a 'Content Disarm & Reconstruction' technology that can prevent the risk of malware infection by removing potential security threats from files and recombining them into safe files. Gartner, a global IT advisory organization, recommends CDR as a solution to attacks in the form of attachments. There is a program using CDR techniques released as open source is called 'Dangerzone'. The program supports the extension of most document files, but does not support the extension of HWP files that are widely used in Korea. In addition, Gmail blocks malicious URLs first, but it does not block malicious URLs in mail systems such as Naver and Daum, so malicious URLs can be easily distributed. Based on this problem, we developed a 'Dangerzone' program that supports the HWP extension to prevent APT attacks, and a Chrome extension that performs URL checking in Naver and Daum mail and blocking banner ads.

• Journal of Oriental Neuropsychiatry
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• v.23 no.3
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• pp.99-116
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• 2012

Objectives : The purpose of this study is to evaluate the effects of Needle-Embedding Therapy on dementia patients. Methods : We recruited 3 dementia patients who have been experiencing memory disorder and orientation disorder. The patients had been evaluated with Mini-Mental State Examination-K (MMSE-K), Global Deterioration Scale (GDS) and Clinical Dementia Rating (CDR). The patients were treated with herbal medication (Sunghyangjunggi-san) and acupuncture. After 15 days, the patients were added to Needle-Embedding Therapy. We measured MMSE-K, GDS and CDR for every 15 days. The effects of additional Needle-Embedding Therapy were compared with the effects of acupuncture and herbal medicine. Results : After Needle-Embedding Therapy was added, Patients' memory and orientation have been improved and the score of MMSE-K ascended. The grade of GDS and CDR were maintained or decreased. Conclusions : This study suggests that Needle-Embedding Therapy is significantly effective on Dementia patients.