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Novel 622Mb/s Burst-mode Clock and Data Recovery Circuits with the Muxed Oscillators  

김유근 (연세대학교 전기전자공학과 초고속정보전송연구실)
이천오 (연세대학교 전기전자공학과 초고속정보전송연구실)
이승우 (연세대학교 전기전자공학과 초고속정보전송연구실)
채현수 (연세대학교 전기전자공학과 초고속정보전송연구실)
류현석 (연세대학교 전기전자공학과 초고속정보전송연구실)
최우영 (연세대학교 전기전자공학과 초고속정보전송연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.28, no.8A, 2003 , pp. 644-649 More about this Journal
Abstract
Novel 622Mb/s burst-mode clock and data recovery (CDR) circuits with muxed oscillators are realized for passive optical network (PON) application. The CDR circuits are implemented with 0.35$\mu\textrm{m}$ CMOS process technology. Lock is accomplished on the first data transition and data are sampled in the optimal point. The experimental results show that the proposed CDR circuits recover the incoming 400Mbps-680Mbps burst mode input data without error.
Keywords
PLL; clock data recovery; burst mode;
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  • Reference
1 A 30 MHz high-speed analog/digital PLL in 2 um CMOS /
[ Kim,B.;Hilman,D.N.;Gray,P.R. ] / Solid-State Circuits Conference
2 A 2GHz 1.6mW Phase Locked Loop /
[ B,Razavi ] / Digest of Technical Papers of the 1996 Symposium on VLSI Circuits
3 /
[ Banu,M.;Dunlop,A.E. ] / Electronics Letters
4 150/30Mb/s CMOS NonOversampled /
[ Alfred E. Dunlop;Wilhelm C. Flscher;Mihai Banu;Thaddeus Gabara ] / Proceedings of the 1995 IEEE International Solid State Circute COnferences