• ETRI Journal
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• v.30 no.2
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• pp.275-281
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• 2008

A 40 Gb/s clock and data recovery (CDR) module for a fiber-optic receiver with improved phase-locked loop (PLL) circuits has been successfully implemented. The PLL of the CDR module employs an improved D-type flip-flop frequency acquisition circuit, which helps to stabilize the CDR performance, to obtain faster frequency acquisition, and to reduce the time of recovering the lock state in the event of losing the lock state. The measured RMS jitter of the clock signal recovered from 40 Gb/s pseudo-random binary sequence ($2^{31}-1$) data by the improved PLL clock recovery module is 210 fs. The CDR module also integrates a 40 Gb/s D-FF decision circuit, demonstrating that it can produce clean retimed data using the recovered clock.

• IEMEK Journal of Embedded Systems and Applications
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• v.12 no.4
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• pp.239-246
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• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.4
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• pp.188-193
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• 2003

This paper describes a novel burst-mode clock and data recovery (CDR) circuit which can be used for 622Mbps burst mode applications. The CDR circuit is basically a phase locked loop (PLL) having two phase detectors (PDs), one for the reference clock and the other for the NRZ data, whose operations are controlled by an external control signal. This CDR was fabricated in a 1-poly 5-metal $0.25{\;}\mu\textrm{m}$ CMOS technology. Jitter generation, burst/continuous mode data receptions were tested. Operational frequency range is 320Mhz~720Mhz and BER is less than 1e-12 for PRBS31 at 622Mhz. For the same data sequence, the extracted clock jitter is less than 8ps rms. Power consumption of 100mW was measured without I/O circuits.

• Journal of the Korean Society of Systems Engineering
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• v.4 no.1
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• pp.45-51
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• 2008

This paper presents template for Critical Design Review(CDR) in case of Urban MAGLEV Program. CDR was executed to confirm for design result based on requirements at last design stage. The integrated template for effective CDR includes requirements, specification and verification items. CDR needs to confirm satisfaction of requirements for design result and define verification method for technical validity. This template will help a consistent and integrated design review. And it is specially useful in huge and complex project.

• Journal of International Academy of Physical Therapy Research
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• v.5 no.1
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• pp.696-700
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• 2014

This study was carried out to identify the influence of continuous physical therapy on long-stay elderly patients. This study classified 92 patients who had been hospitalized for one year into experimental group who continued to perform physical therapy and control group who did not conduct physical therapy and these two groups were classified into 0.5 point-questionable group, 1 point-mild dementia group, and 2 point-moderate dementia group based on the Clinical Dementia Rating Scale(CDR) when they were hospitalized in order to analyze the changes at the early stage of hospitalization and after one year has passed. As a result, it was appeared that both in CDR 0.5-point subgroup of questionable group and in CDR 1-point subgroup of mild dementia group, CDR was statistically significantly reduced in the experimental group whose physical therapy was continuously performed than in the control group whose physical therapy was not performed(p<.05) and that there was no significant difference in changes in the CDR between experimental group and control group in CDR 2-point group, which is a moderate dementia group.

• Nuclear Engineering and Technology
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• v.50 no.5
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• pp.673-682
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• 2018

One of the most widely used methods to estimate core damage during a nuclear power plant accident is containment radiation measurement. The evolution of severe accidents is extremely complex, leading to uncertainty in the containment dose rate (CDR). Therefore, it is difficult to accurately determine core damage. This study proposes to conduct uncertainty analysis of CDR for core damage assessment. First, based on source term estimation, the Monte Carlo (MC) and point-kernel integration methods were used to estimate the probability density function of the CDR under different extents of core damage in accident scenarios with late containment failure. Second, the results were verified by comparing the results of both methods. The point-kernel integration method results were more dispersed than the MC results, and the MC method was used for both quantitative and qualitative analyses. Quantitative analysis indicated a linear relationship, rather than the expected proportional relationship, between the CDR and core damage fraction. The CDR distribution obeyed a logarithmic normal distribution in accidents with a small break in containment, but not in accidents with a large break in containment. A possible application of our analysis is a real-time core damage estimation program based on the CDR.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• IMMUNE NETWORK
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• v.3 no.2
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• pp.89-95
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• 2003

Background: Unusually high amounts of N region addition and CDR3 length diversity were found in immunoglobulin (Ig) light chain Vk and Jk joins in patients with rheumatoid arthritis (RA). We sought to determine whether this finding is due to excessive activity of the enzyme responsible for N region addition (terminal deoxynucleotidyl transferase [TdT]) in B lineage cells in bone marrow or from positive antigenic selection of B cells with long CDR3 lengths. Methods: We used FACS to isolate $IgM^+/IgD^+$ B cells (predominantly naive) and $IgM^-/IgD^-$ B cells (predominantly class-switched) B cells from peripheral blood of a patient with RA known to have enrichment for long Vk CDR3s and from that of two normal controls. RT-PCR of VkIII transcripts was performed, followed by sequencing of individual cDNA clones. We analyzed the CDR3 lengths and N region additions in 97 clones. Results: There was enrichment for long CDR3 lengths (11 or 12 amino acids) in both $IgM^+/IgD^+$ and $IgM^-/IgD^-$ B cells in RA compared to B cell subsets in the normal controls. The $IgM^+/IgD^+$ B cell subset in RA was markedly enriched for N region addition and was similar to that seen in the $IgM^-/IgD^-$ subset. Conclusion: These data suggest that enrichment for N region addition and long CDR3 lengths in RA may result from unusually high or prolonged activity of TdT in bone marrow.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.10
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• pp.87-95
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• 2014

This paper describes a dual channel receiver design for CIS interfaces. Each channel includes CTLE(Continuous Time Linear Equalizer), sampler, deserializer and clocking circuit. The clocking circuit is composed of PLL, PI and CDR. Fast lock acquisition time, short latency and better jitter tolerance are achieved by adding OSPD(Over Sampling Phase Detector) and FSM(Finite State Machine) to PI-based CDR. The CTLE removes ISI caused by channel with -6 dB attenuation and the lock acquisition time of the CDR is below 1 baud period in frequency offset under 8000ppm. The voltage margin is 368 mV and the timing margin is 0.93 UI in eye diagram using 65 nm CMOS technology.

• Journal of Sensor Science and Technology
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• v.12 no.4
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• pp.191-197
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• 2003

Due to explosive increase of internet usage, broadband data transmission using optical fibers is broadly used. In order to decrease distortion during long distance transmission, the optical signal need to be restored, typically, by converting the optical signal into the electrical signal. The optical signal is converted into the electrical signal using a photo-diode, and then a clock-and-recovery (CDR) circuit is used to recover the clock and retime the data. In this study, a clock-and-data recovery circuit has been designed using a standard 1.8 V $0.18\;{\mu}m$ CMOS process. With this CDR circuit, the improved phase detector and charge pump have been utilized. Also, by using a ring oscillator, the CDR circuit can recover clock and data from broadband multi-rate data ranging between 750 Mb/s and 2.85 Gb/s.