• Proceedings of the Korean Society of Life Science Conference
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• 2007.10a
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• pp.84.2-84.2
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• 2007

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• Journal of the Korean Magnetics Society
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• v.5 no.5
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• pp.854-857
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• 1995

We have studied the temperature dependence of the $^{1}H$ NMR spin-lattice relaxation for the impure $CuF_{2}.2H_{2}O$ over a temperature range from 77 K to room temperature. We find that the remperature dependence of the $^{1}H$ spin-lattice relaxation is dominated by the eletron spin-flip and the Raman process of eletron spin-lattice relaxation. The electron spin-flip exchange energy was calculated to be $1.8(\pm0.04)$ K.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.53-58
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• 2013

An innovative packaging solution, Flip Chip with Copper (Cu) Column bond on lead (BOL) Enhanced Process (fcCuBE$^{(R)}$) delivers a cost effective, high performance packaging solution over typical bond on capture pad (BOC) technology. These advantages include improved routing efficiency on the substrate top layer thus allowing conversion functionality; furthermore, package cost is lowered by means of reduced substrate layer count and removal of solder on pad (SOP). On the other hand, as electronic packaging technology develops to meet the miniaturization trend from consumer demand, reliability testing will become an important issue in advanced technology area. In particular, electromigration (EM) of flip chip bumps is an increasing reliability concern in the manufacturing of integrated circuit (IC) components and electronic systems. This paper presents the results on EM characteristics on BOL and BOC structures under electrical current stressing in order to investigate the comparison between two different typed structures. EM data was collected for over 7000 hours under accelerated conditions (temperatures: $125^{\circ}C$, $135^{\circ}C$, and $150^{\circ}C$ and stress current: 300 mA, 400 mA, and 500 mA). All samples have been tested without any failures, however, we attempted to find morphologies induced by EM effects through cross-sectional analysis and investigated the interfacial reaction characteristics between BOL and BOC structures under current stressing. EM damage was observed at the solder joint of BOC structure but the BOL structure did not show any damage from the effects of EM. The EM data indicates that the fcCuBE$^{(R)}$ BOL Cu column bump provides a significantly better EM reliability.

• Journal of the Korean Ceramic Society
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• v.50 no.3
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• pp.238-243
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• 2013

We investigated the effect of Pb-metal filler added to a hybrid paste(PbO-$Bi_2O_3-B_2O_3$-ZnO glass frit and Pb-powder), for joining flip-chip sat lower temperatures than normal. The glass transition temperature was detected at $250^{\circ}C$ and the softening point occurred at $330^{\circ}C$. As the temperature increased, the specific density decreased due to the volatility of the Pb-metal and boron component in the glass. When the glass was heat-treated at $350^{\circ}C$ for 5 min, XRD results revealed a crystalline $Pb_4Bi_3B_7O_{19}$ phase that had been initiated by the addition of Pb-filler in the hybrid paste. The addition of the Pb-metal filler caused are action between the Pb-metal and glass that accelerated the formation of the liquid phase. The liquid phase that formed, promoted bonding between the flip-chip substrate sat lower temperature.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.12
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• pp.1120-1127
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• 2013

In this paper, novel chip-on-chip(CoC) flip-chip bump structures using chip-on-wafer(CoW) process technology are proposed, designed and fabricated, and their microwave frequency responses are analyzed. With conventional bumps of Cu pillar/SnAg and Cu pillar/Ni/SnAg and novel Polybenzoxazole(PBO)-passivated bumps of Cu pillar/SnAg, Cu pillar/Ni/SnAg and SnAg with the deposition option of $2^{nd}$ Polyimide(PI2) layer on the wafer, 10 kinds of CoC samples are designed and their frequency responses up to 20 GHz are investigated. The measurement results show that the bumps on the wafers with PI2 layers are better for the batch flip-chip process and have average insertion loss of 0.14 dB at 18 GHz. The developed bump structures for chips with fine-pitch pads show similar or slightly better insertion loss of 0.11~0.14 dB up to 18 GHz, compared with that of 0.13~0.17 dB of conventional bump structures in this study, and we find that they could be utilized in various microwave packages for high integration density.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.1
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• pp.1-6
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• 2014

Flip chip bonded LED packages possess lower thermal resistance than wire bonded LED packages because of short thermal path. In this study, thermal and bonding properties of flip chip bonded high brightness LED were evaluated for Au-Sn thermo-compression bonded LEDs and Sn-Ag-Cu reflow bonded LEDs. For the Au-Sn thermo-compression bonding, bonding pressure and bonding temperature were 50 N and 300oC, respectively. For the SAC solder reflow bonding, peak temperature was $255^{\circ}C$ for 30 sec. The shear strength of the Au-Sn thermo-compression joint was $3508.5gf/mm^2$ and that of the SAC reflow joint was 5798.5 gf/mm. After the shear test, the fracture occurred at the isolation layer in the LED chip for both Au-Sn and SAC joints. Thermal resistance of Au-Sn sample was lower than that of SAC bonded sample due to the void formation in the SAC solder.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.58-64
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• 2013

In this paper, two new flip-flop circuits with PCRAM latches that are FF-1 and FF-2, respectively, are proposed not to waste leakage during sleep time. Unlike the FF-1 circuit that has a normal PCRAM latch, the FF-2 circuit has a selective write latch that can reduce the switching activity in writing operation to save switching power at sleep-in moment. Moreover, a sequential sleep-in control is proposed to reduce the rush current peak that is observed at the sleep-in moment. From the simulation of storing '000000' to the PCRAM latch, we could verify that the proposed FF-1 and FF-2 consume smaller power than the conventional 45-nm FF if the sleep time is longer than $465{\mu}s$ and $95{\mu}s$, respectively, at $125^{\circ}C$. For the rush current peak, the sequential sleep-in control could reduce the current peak as much as 77%.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.7-15
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• 2006

In-situ observation of electromigration in thin film pattern of 63Sn-37Pb solder was performed using a scanning electron microscope system. The 63Sn-37Pb solder had the incubation stage of electromigration for edge movement when the current density of $6.0{\times}10^{4}A/cm^2$ was applied the temperature between $90^{\circ}C\;and\;110^{\circ}C$. The major diffusion elements due to electromigration were Pb and Sn at temperatures of $90-110^{\circ}C\;and\;25-50^{\circ}C$, respectively, while no major diffusion of any element due to electromigration was detected when the test temperature was $70^{\circ}C$. The reason was that both the elements of Sn and Pb were migrated simultaneously under such a stress condition. The existence of the incubation stage was observed due to Pb migration before Sn migration at $90-110^{\circ}C$. Electromigration behavior of 63Sn-37Pb solder had an incubation time in common for edge drift and void nucleation, which seemed to be related the lifetime of flip chip solder bump. Diffusivity with $Z^*$(effective charges number) of Pb and Sn were strongly affect the electromigration-induced major diffusion element in SnPb solder by temperature, respectively.

• Korean Journal of Materials Research
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• v.6 no.7
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• pp.700-708
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• 1996

Electroless plating technique was utilized to flip chip bonding to improve surface mount characteristics. Each step of plating procedure was studied in terms pf pH, plating temperature and plating time. Al patterned 4 inch Si wafers were used as substrstes and zincate was used as an activation solution. Heat treatment was carried out for all the specimens in the temperature range from room temperature to $400^{\circ}C$ for $30^{\circ}C$ minutes in a vacuum furnace. Homogeneous distribution of Zn particles of size was obtained by the zincate treatment with pH 13 ~ 13.5, solution concentration of 15 ~ 25% at room temperature. The plating rates for both Ni-P and Au electroless plating steps increased with increasing the plating temperature and pH. The main crystallization planes of the plated Au were found to be (111) a pH 7 and (200) and (111) at pH 9 independent of the annealing temperature.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1345-1352
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• 2014

Bus architecture of SoC has been replaced by NoC in recent years. Noc uses the multi-clock domains to transmit and receive data between neighbor network interfaces and they have same frequency, but a phase difference because of clock skew. So a synchronizer is used for a mesochronous frequency in interconnection between network interfaces. In this paper the metastability is defined and analyzed in a D latch and a D flip-flop to search the possibilities that data can be lost in the process of sending and receiving data between interconnects when a local frequency and a transmitted frequency have a phase difference. 180nm CMOS model parameter and 1GHz are used to simulate them in HSpice. The simulation results show that the metastability happens in a latch and a flip-flop when input data change near the clock edges and there are intermediate states for a longer time as input data change closer at the clock edge. And the next stage can lose input data depending on environmental conditions such as temperature, processing variations, power supply, etc. The simulation results are very useful to design a mescochronous synchronizer for NoC.