• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.1
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• pp.1-7
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• 2019

In this paper, a design technique using a bypass capacitor is proposed to improve the antenna efficiency of an inverted-F antenna (IFA) with a band stop matching circuit (BSMC). The proposed antenna operates in the LTE bands 26 and 5(814~ 894 MHz). The bandwidth of the IFA is expanded from 803~863 MHz to 800~888 MHz using the impedance change caused by the BSMC. To enhance the antenna efficiency in the expanded frequency band, the bypass capacitor is applied to the IFA with the BSMC. The bypass capacitor improves the efficiency of the antenna by reducing the current variation of the IFA with the BSMC. The proposed antenna has a bandwidth of 804~895 MHz and the antenna efficiency increases by more than 10 % in the extended frequency band by using the bypass capacitor.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.4 no.3 s.8
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• pp.73-78
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• 2005

In this paper, a bandpass filter with excellent cut off characteristic due to transmission zero using bypass coupling capacitor and with superior harmonic characteristic by interdigital capacitor is suggested. The measurement results for SIR bandpass filter with bypass coupling capacitor and interdigital capacitor show that the insertion loss is less than 1.9 dB and the return loss is better than 15.4 dB with 4.2 % bandwidth at the center frequency of 5.78 GHz.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.4
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• pp.361-367
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• 2014

This paper is related to a new solar power conditioner for a built-in step-up chopper function. In the first step-up chopper proposed solar PV power conditioner for mutually connected in series with the input voltage of the bypass diodes are respectively connected to the positive terminal should install the mutual boosting chopper diode connected in series with the boost chopper switching element between the two power supply and at the same time the first and the second was connected to a second diode and a resonance inductor and a snubber capacitor in series with each other. And the common connection point between the bypass diode and the step-up chopper and the step-up chopper diode common connection point of the switching elements of the input voltage was set to the boost inductor for storing energy. In addition, between the step-up chopper and the step-up chopper diode and a switching element of a joint connection point of the first auxiliary diode and the second common connection point of the auxiliary diode was provided, the resonance capacitor. Between the step-up chopper and the step-up chopper diode and a switching element of a joint connection point and the common connection point of the resonance inductor snubber capacitor and connecting the third secondary diode, between two power supply lines is characterized by configuring the DC link capacitor bus lines in parallel. Therefore, it is possible to suppress the switching loss through, DC link bus lines, as well as there could seek miniaturization and weight reduction of the power conditioner itself by using a common capacitor of the non-polar non-polar electrolytic capacitor having a capacitor, the service life of the circuit can be extended and it is possible to greatly reduce the loss can be greatly improve the reliability of the product and the operation of the product itself.

• Journal of Power Electronics
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• v.15 no.2
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• pp.567-575
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• 2015

An improvement in the current fed parallel resonant half bridge (CFPRHB) circuits used in fluorescent lamp electronic ballasts is provided in this paper. The CFPRHB belongs to the self-oscillating family which includes the current fed push-pull and series resonant inverters, most of which are used in instant-start applications. However, many failure modes are related to the bypass capacitor according to an analysis of failed samples. In this paper, the operating functions of the existing topology in the steady state are analyzed and the main root cause of failure modes has been found. Comparisons between the two topologies are conducted in terms of the voltage stress of the bypass capacitor as well as the thermal and performance of the ballasts to verify the advantages of the proposed topology. It is found that the improved topology is capable of enhancing the reliability and reducing the cost of products without having a negative influence on the system performance.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.2
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• pp.840-845
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• 2013

In this paper, the broadband frequency double down-converter based on LC filter technologies has been designed and implemented, and its performances are introduced. The Designed frequency double down-converter is consisted with a low-noise amplifier, mixer, IF amplifier, LC filter, DC-block capacitor and RF-bypass capacitor. Especially, instead of active devices of a typical converter, the suggested converter designed using passive devices to provide both low-power consumption and low-cost model. As results of the measurement, the implemented frequency double down-converter realizes the broadband performance with the bandwidth of 100MHz (13~113MHz) at the center frequency of 63MHz, and its gain is approximately 40dB.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.2
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• pp.801-807
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• 2012

In this paper, design and implementation of frequency down converter based on LC filter technic. Single frequency down converter, designed a low-noise amplifier, mixer, IF amplifier, LC filter was configured. And it is composed of DC block capacitors and RF bypass capacitor. LC filter, replace it with the IC reduced the power and realized low cost. The gain of single down converter is about 10dBm and realized by 18MHz bandwidth at 70MHz band.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.179-185
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• 2005

This paper presents a novel circuit topology of a high efficiency single-phase power conditioner. This power conditioner is composed of time-sharing sinewave absolute pulse width modulated boost chopper with a bypass diode in the first power processing stage and time-sharing sinewave pulse width modulated full-bridge inverter in the second power processing stage operated by time-sharing dual mode pulse pattern control scheme. The unique operating principle of the two power processing stage with time-sharing dual mode sinewave modulation scheme is described with a design example. This paper proposes also a sinewave tracking voltage controlled soft switching PWM boost chopper with a passive auxiliary edge-resonant snubber. The new conceptual operating principle of this novel power conditioner related to new energy utilization system is presented and discussed through the experimental results.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.195-204
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• 2015

In this paper, the development of a cost-effective active power filter/uninterruptible power supply (APF/UPS) system with seamless mode transfer is described. The proposed scheme employs a pulse-width-modulation (PWM) voltage-source inverter and has two operational modes. First, when the source voltage is normal, the system operates as an APF, which compensates for the harmonics and power factor while boosting the DC-link voltage to be ready for the disturbance, without an additional DC charging circuit. A simple algorithm to detect the load current harmonics is also proposed. Second, when the source voltage is out of the normal range (owing to sag, swell, or outage), it operates a UPS, which controls the output voltage constantly by discharging the DC-link capacitor. Furthermore, a seamless transfer method for the single-phase inverter between the APF mode and the UPS mode is also proposed, in which an IGBT switch with diodes is used as a static bypass switch. Dissimilar to a conventional SCR switch, the IGBT switch can implement a seamless mode transfer. During the UPS operation, when the source voltage returns to the normal range, the system operates as an APF. The proposed system has good transient and steady-state response characteristics. The APF, charging circuit, and UPS systems are implemented in one inverter system. Finally, the validity of the proposed scheme is investigated with simulated and experimental results for a prototype APF/UPS system rated at 3 kVA.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.289-294
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• 2008

A 77 GHz 3-stage low noise amplifier (LNA) employing one common source and two cascode stages is developed using $0.13{\mu}m$ CMOS process. To compensate for the low gain which is caused by lossy silicon substrate and parasitic element of CMOS transistor, positive feedback technique using parasitic inductance of bypass capacitor is adopted to cascode stages. The developed LNA shows gain of 7.2 dB, Sl1 of -16.5 dB and S22 of -19.8 dB at 77 GHz. The return loss bandwidth of LNA is 71.6 to 80.9 GHz (12%). The die size is as small as $0.7mm\times0.8mm$ by using bias line as inter-stage matching networks. This LNA shows possibility of 77 GHz automotive RADAR system using $0.13{\mu}m$ CMOS process, which has advantage in cost compared to sub-100 nm CMOS process.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.3
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• pp.312-318
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• 2016

This paper presents a 2-6 GHz GaN HEMT power amplifier monolithic microwave integrated circuit (MMIC) with bridged-T all-pass filters and output-reactance-compensation shorted stubs using the $0.25{\mu}m$ GaN HEMT foundry process that is developed by WIN Semiconductors, Inc. The bridged-T filter is modified to mitigate the bandwidth degradation of impedance matching due to the inherent channel resistance of the transistor, and the shorted stub with a bypass capacitor minimizes the output reactance of the transistor to ease wideband load impedance matching for maximum output power. The fabricated power amplifier MMIC shows a flat linear gain of 20 dB or more, an average output power of 40.1 dBm and a power-added efficiency of 19-26 % in 2 to 6 GHz, which is very useful in applications such as communication jammers and electronic warfare systems.