• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1959-1960
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• 2008

The Logic Built In Self Test (LBIST) technique is substantially applied in chip design in most many semiconductor company in despite of unavoidable overhead like an increase in dimension and time delay occurred as it used. Currently common LBIST software uses the MISR (Multiple Input Shift Register) However, it has many considerations like defining the X-value (Unknown Value), length and number of Scan Chain, Scan Chain and so on for analysis of result occurred in the process. So, to solve these problems, common LBIST software provides the solution method automated. Nevertheless, these problems haven't been solved automatically by Tri-state Bus in logic circuit yet. This paper studies the algorithm that it also suggest algorithm that reduce additional circuits and time delay as matching of pattern about 2-type circuits which are CUT(circuit Under Test) and additional circuits so that the designer can detect the wrong location in CUT: Circuit Under Test.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.723-728
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• 1999

In this paper, we designed a Circular Path Built-In Self Test circuit and embedded it into a simple 8-bit microprocessor. Register cells of the microprocessor have been modified into Circular Path register cells and each register cells have been connected to form a scan chain. A BIST controller has been designed for controlling BIST operations and its operation has been verified through simulation. The BIST circuit described in this paper has increased size overhead of the microprocessor by 29.8% and delay time in the longest delay path from clock input to output by 2.9㎱.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.1069-1072
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• 1998

Recently the development of design and automation technology and manufacturing method, has reduced the cost of chip, but it becomes more difficult to test IC chip because test technique doesn't keep up with these techniques. In case of IC testing, obtaining test vectors to be able to detect good chip or bad one is very important, but according to increasing complexity, it is very complex and difficult. Another problem is that during testing, there could be capability of physical and electrical damage on chip. Also there is difficulty in synchronization between CUT (circuit under test) and Test equipment〔1〕. Because of these difficulties, built in self test has been proposed. Not only obtaining test vectors but also reducing test time becomes hot issues nowadays. This paper presents a new test BIST(built in self test) method. Proposed BIST implementation reduces test time and obtains high fault coverage. By searching internal nodes in which are inserted test_point_cells〔2〕and allocating TPG(test pattern generation) stages, test length becomes much shorter.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2004년도 춘계종합학술대회
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• pp.635-641
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• 2004

본 논문에서는 802.113 무선 근거리 통신망(wireless LAM)용 5.25GHz 저잡음 증폭기(LNA)에 대해 고가 장비를 사용하지 않고도 전압이득, 잡음지수 및 입력 임피던스를 측정할 수 있는 새로운 형태의 고주파 81ST(Built-In Self-Test, 자체내부검사)회로 설계 및 검사 기술을 제안한다. 본 연구에서 제작된 BIST 회로는 기존의 고가 검사 장비 대신 고주파 회로의 결함검사나 성능검사에 적용될 수 있다. 이러한 BIST 회로는 1V의 공급전압에서 동작하며, 0.18$\mu\textrm{m}$ SiGe 공정으로 제작되어 있다. 이러한 접근방법은 입력 임피던스 정합과 출력 전압 측정을 이용한다. 본 방법에서는 DUT(Device Under Test: 검사대상이 되는 소자)와 BIST 회로가 동일 칩 상에 설계되어 있기 때문에 측정할 때 단지 디지털 전압계와 고주파 전압 발생기만이 필요하며, 측정이 간단하고 비용이 저렴하다는 장점이 있다. BIST 회로가 차지하는 면적은 LNA가 차지하는 전체면적의 약 18%에 불과하다.

• ETRI Journal
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• 제37권4호
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• pp.787-792
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• 2015

To accomplish a high-speed test on low-speed automatic test equipment (ATE), a new instruction-based fully programmable memory built-in self-test (BIST) is proposed. The proposed memory BIST generates a highspeed internal clock signal by multiplying an external low-speed clock signal from an ATE by a clock multiplier embedded in a DRAM. For maximum programmability and small area overhead, the proposed memory BIST stores the unique sets of instructions and corresponding test sequences that are implicit within the test algorithms that it receives from an external ATE. The proposed memory BIST is managed by an external ATE on-the-fly to perform complicated and hard-to-implement functions, such as loop operations and refresh-interrupts. Therefore, the proposed memory BIST has a simple hardware structure compared to conventional memory BIST schemes. The proposed memory BIST is a practical test solution for reducing the overall test cost for the mass production of commodity DDRx SDRAMs.

• 전자공학회지
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• 제19권5호
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• pp.108-116
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• 1992

• 한국통신학회논문지
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• 제30권4A호
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• pp.328-335
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• 2005

본 논문에서는 내장된 메모리의 자체 테스트를 통한 메모리 고장 유무 확인과 더불어 메인 메모리의 고장난 부분을 여분의 메모리로 재배치하여 사용자로 하여금 고장난 메모리를 정상적인 메모리처럼 사용할 수 있도록 BISR(Build-In Self Repair) 설계 및 구현을 하였다. 메인 메모리를 블록 단위로 나누어 고장난 셀의 블록 전체를 재배치하는 방법을 사용하였으며, BISR은 BIST(Build-In Self Test) 모듈과 BIRU(Build-In Remapping Unit) 모듈로 구성된다. 실험결과를 통해 고장난 메모리를 여분의 메모리로 대체하여 사용자가 메모리를 사용함에 있어서 투명하게 제공하는 것을 확인 할 수 있다.

• ETRI Journal
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• 제35권5호
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• pp.808-818
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• 2013

Programmable memory built-in self-test (PMBIST) is an attractive approach for testing embedded memory. However, the main difficulties of the previous works are the large area overhead and low flexibility. To overcome these problems, a new flexible PMBIST (FPMBIST) architecture that can test both single-port memory and dual-port memory using various test algorithms is proposed. In the FPMBIST, a new instruction set is developed to minimize the FPMBIST area overhead and to maximize the flexibility. In addition, FPMBIST includes a diagnostic scheme that can improve the yield by supporting three types of diagnostic methods for repair and diagnosis. The experiment results show that the proposed FPMBIST has small area overhead despite the fact that it supports various test algorithms, thus having high flexibility.

• 대한전자공학회논문지SD
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• 제40권2호
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• pp.126-136
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• 2003

본 논문에서는 최근 많은 연구대상이 되고 있는 oscillation test methodology (OTM)의 파라메트릭 고장에 대한 커버리지를 높일 수 있는 방법을 제안한다. OTM은 테스트 입력신호가 별도로 필요없는 장점으로 인해 효율적인 built-in self test (BIST) 기술로서도 많은 관심의 대상이 되어 왔다. 그러나 아직 여러 가지 면에서 좀더 연구개발이 필요한 상태이며, 따라서 본 논문에서는 그 성능을 향상시킬 수 있는 방안을 제안한다.

• 전자공학회논문지C
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• 제35C권8호
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• pp.10-22
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• 1998

To handle the density increase of SRAMs, a new parallel testing methodology based on built-in self test (BIST) is developed, which allows to access multiple cells simultaneously. The main idea is that a march algorithm is dperformed concurently in each baisc marching block hwich makes up whole memory cell array. The new parallel access method is very efficient in speed and reuqires a very thny hardware overhead for BIST circuitry. Results show that the fault coverage of the applied march algorithm can be achieved with a lower complexity order. This new paralle testing algorithm tests an .root.n *.root.n SRAM which consists of .root.k * .root.k basic marching blocks in O(5*.root.k*(.root.k+.root.k)) test sequence.