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SRAM Reuse Design and Verification by Redundancy Memory  

Shim Eun sung (숭실대학교 대학원 컴퓨터학과)
Chang Hoon (숭실대학교 컴퓨터학과 컴퓨터구조 연구실)
Publication Information
The Journal of Korean Institute of Communications and Information Sciences / v.30, no.4A, 2005 , pp. 328-335 More about this Journal
Abstract
bIn this paper, built-in self-repair(BISR) is proposed for semiconductor memories. BISR is consisted of BIST(Buit-in self-test) and BIRU(Built-In Remapping Uint). BIST circuits are required not oがy to detect the presence of faults but also to specify their locations for repair. The memory rows are virtually divided into row blocks and reconfiguration is performed at the row block level instead of the traditional row level. According to the experimental result, we can verify algorithm for replacement of faulty cell.
Keywords
BISR; BIST; SRAM; SOC; Embedded Memory;
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