• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.11
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• pp.3227-3233
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• 2009

A method for performing Boolean resubstitution is proposed. This method is efficiently implemented using division matrix. It begins by creating an algebraic division matrix from given two logic expressions. By introducing Boolean properties and adding literals into the algebraic division matrix, we make the Boolean division matrix. Using this extended division matrix, Boolean substituted expressions are found. Experimental results show the improvements in the literal counts over well-known logic synthesis tools for some benchmark circuits.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.3
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• pp.1-6
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• 1976

In this paper, a method of test pattern generation for the functional failure in both combinational and sequentlal logic networks by using exterded Boole an difference is proposed. The proposed technique provides a systematic approach for the test pattern generation procedure by computing Boolean difference of the Boolean function that represents the Logic network for which the test patterns are to be generated. The computer experimental results show that the proposed method is suitable for both combinational and asynchronous sequential logic networks. Suitable models of clocked flip flops may make it possible for one to extend this method to synchronous sequential logic networks.

• The KIPS Transactions:PartA
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• v.15A no.1
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• pp.9-16
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• 2008

This paper presents a new Boolean extraction technique for logic synthesis. This method extracts two-cube Boolean subexpression pairs from each logic expression. It begins by creating two-cube array, which is extended and compressed with complements of two-cube Boolean subexpressions. Next, the compressed two-cube array is analyzed to extract common subexpressions for several logic expressions. The method is greedy and extracts the best common subexpression. Experimental results show the improvements in the literal counts over well-known logic synthesis tools for some benchmark circuits.

• Journal of the Korea Computer Industry Society
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• v.7 no.5
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• pp.473-480
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• 2006

Extraction is tile most important step in global minimization. Its approache is to identify and extract subexpressions, which are multiple-cubes or single-cubes, common to two or more expressions which can be used to reduce the total number of literals in a Boolean network. Extraction is described as either algebraic or Boolean according to the trade-off between run-time and optimization. Boolean extraction is capable of providing better results, but difficulty in finding common Boolean divisors arises. In this paper, we present a new method for Boolean extraction to remove the difficulty. The key idea is to identify and extract two-cube Boolean subexpression pairs from each expression in a Boolean network. Experimental results show the improvements in the literal counts over the extraction in SIS for some benchmark circuits.

• Journal of Korea Society of Industrial Information Systems
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• v.16 no.5
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• pp.9-19
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• 2011

In many instances a concise form of logic is often required for building today's complex systems. The method described in this paper can be used for a wide range of industrial applications that requires Boolean type of logic minimization. Unlike some of the previous logic minimization methods, the proposed method can be used to better gain insights into the logic minimization process. Based on the decimal valued matrix, the method described here can be used to find an exact minimized solution for a given Boolean function. It is a visual based method that primarily relies on grouping the cell values within the matrix. At the same time, the method is systematic to the extent that it can also be computerized. Constructing the matrix to visualize a logic minimization problem should be relatively easy for the most part, particularly if the computer-generated graphs are accompanied.

• The Journal of Korean Association of Computer Education
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• v.15 no.1
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• pp.65-72
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• 2012

Generally, a logic function has many factored forms. The problem of finding more compact factored form is one of the basic operations in logic synthesis. In this paper, we present a new method for factoring Boolean functions to assist in educational logic designs. Our method for factorization is to implement two-cube Boolean division with supports of an expression. The number of literals in a factored form is a good estimate of the complexity of a logic function. Our empirical evaluation shows the improvements in literal counts over previous other factorization methods.

• Korean Journal of Logic
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• v.9 no.2
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• pp.1-30
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• 2006

This paper investigates algebraic semantics for some weak Boolean (wB) logics, which may be regarded as left-continuous t-norm based logics (or monoidal t-norm based logics (MTLs)). We investigate as infinite-valued logics each of wB-LC and wB-sKD, and each corresponding first order extension $wB-LC\forall$ and $wB-sKD\forall$. We give algebraic completeness for each of them.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.337-340
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• 2000

In this paper, we put forth a procedure that target low power logic synthesis based on XOR representation of Boolean functions, and the results of synthesis procedure are a multi-level XOR form with minimum switching activity. Specialty, this paper show a method to extract the common cubes or kernels by Boolean matrix and rectangle covering, and to estimate the power consumption in terms of the extracted common sub-functions.

• 전기의세계
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• v.28 no.8
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• pp.57-65
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• 1979

This paper is concerned with not only the transformation of the logic diagrams to the NAND and the NOR forms but also the inverse transformation deriving the simple Boolean function from a logic diagram. The conversions of the algebraic expression from the AND, OR and NOT operations to the NAND and the NOR operations are usually quite complicated, because they involve a large number of repeated applications of De Morgan's Theorem and the other logic relations. For the derivation of the Boolean function, it becomes difficult because the Boolean function is determined from the De Morgan's theorem in consecutive order until the output is expressed in terms of input variables (9). But, these difficulties are avoided by the use of new techniques, called the TWO-NOTs method and the MOVING-NOT method, that are presented in this paper.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.849-852
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• 2005

A factorization is an extremely important part of multi-level logic synthesis. The number of literals in a factored from is a good estimate of the complexity of a logic function, and can be translated directly into the number of transistors required for implementation. Factored forms are described as either algebraic or Boolean, according to the trade-off between run-time and optimization. A Boolean factored form contains fewer number of literals than an algebraic factored form. In this paper, we present a new method for a Boolean factorization. The key idea is to identify two-cube Boolean subexpression pairs from given expression. Experimental results on various benchmark circuits show the improvements in literal counts over the algebraic factorization based on Brayton's co-kernel cube matrix.