DOI QR코드

DOI QR Code

Boolean Extraction Technique Using Two-cube Divisors and Complements

2-큐브 제수와 보수에 의한 공통 논리식 산출

  • 권오형 (한서대학교 인터넷공학과) ;
  • 오임걸 (한서대학교 인터넷공학과)
  • Published : 2008.02.29

Abstract

This paper presents a new Boolean extraction technique for logic synthesis. This method extracts two-cube Boolean subexpression pairs from each logic expression. It begins by creating two-cube array, which is extended and compressed with complements of two-cube Boolean subexpressions. Next, the compressed two-cube array is analyzed to extract common subexpressions for several logic expressions. The method is greedy and extracts the best common subexpression. Experimental results show the improvements in the literal counts over well-known logic synthesis tools for some benchmark circuits.

본 논문에서는 논리합성을 위한 공통식 추출 방법을 새롭게 제안한다. 제안하는 방법은 주어진 각 논리식들에서 2개의 큐브만으로 구성된 2-큐브 논리식 쌍을 추출한다. 2개의 큐브로 구성된 논리식 쌍들로부터 2-큐브 행렬을 만들고, 여기에 2-큐브 논리식의 보수를 추가하여 확장된 2-큐브 행렬과 압축 2-큐브 행렬을 만든다. 다음, 공통식 추출을 위해 압축 2-큐브 행렬을 분석한다. 그리디 방법(greedy method)에 의해 가장 많은 리터럴 개수를 줄일 수 있는 공통식을 선택한다. 실험결과 여러 벤치마크 회로에 대하여 제안한 방법을 논리회로 합성도구에 활용할 경우 기존 합성도구보다 리터럴 개수를 줄일 수 있음을 보였다.

Keywords

References

  1. R. K. Brayton and C. McMullen,'The Decomposition and Factorization of Boolean Epressions,' Proc. ISCAS, pp.49-54, 1982
  2. R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang,'MIS: A Multiple-Level Logic Optimization System,' IEEE Trans. CAD, Vol. 6, No. 6, pp.1062-1081, 1987 https://doi.org/10.1109/TCAD.1987.1270347
  3. E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, R. K., and A. Sangiovanni-Vincentelli,'Sequential Circuit Design Using Synthesis and Optimization,' Proc. ICCD, pp.328-333, 1992
  4. W.-J. Hsu and W.-Z. Shen,'Coalgebraic Division for Multilevel Logic Synthesis,' Proc. of DAC, pp.438-442, 1992
  5. C. Yang and M. Ciesielski,'BDS: A Boolean BDD-Based Logic Optimization System,' IEEE Trans. CAD, Vol. 21, No. 7, pp.866-876, 2002 https://doi.org/10.1109/TCAD.2002.1013899
  6. D. Wu and J. Zhu,'FBDD: A Folded Logic Synthesis System,' Technical Report TR-07-01-05, University of Toronto, July, 2005
  7. S. Nagayama and T. Sasao,'Representation of Elementary Functions Using Edge-Valued MDDs,' Proc. of the 37th International Symposium on Multiple-Valued Logic(ISMVL '07), pp.5-11, 2007
  8. J. Rajski and J. Vasudevamurthy,'The Testability-Preserving Concurrent Decomposition and Factorization of Boolean Expressions,' IEEE Trans. CAD, Vol. 11, No. 6, pp.778-793, 1992 https://doi.org/10.1109/43.137523
  9. D. Wu, and J. Zhu,'BDD-based Two Variable Sharing Extraction,' Proc. ASPDAC, pp.1031-1034, 2005
  10. O.-H. Kwon,'Boolean Extraction Technique for Multiple-level Logic Optimization,' Proc. ISCAS, Vol. 4, pp.684-687, 2003
  11. J. Cong and K. Minkovich,'Optimality Study of Logic Synthesis for LUT-Based FPGAs,' IEEE Trans. CAD, Vol. 26, No. 2, pp.230-239, 2007 https://doi.org/10.1109/TCAD.2006.887922
  12. A. C. Ling, P. Singh, and S. D. Brown,'FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiablity,' IEEE Trans. CAD, Vol. 26, No. 7, pp.1196-1210, 2007 https://doi.org/10.1109/TCAD.2007.891362
  13. S. Yang,'Logic Synthesis and Optimization Benchmarks User Guide Version 3.0,' Technical Report, Microelectronics Center of North Carolina, 1991