A Boolean Logic Extraction for Multiple-level Logic Optimization

다변수 출력 함수에서 공통 논리식 추출

Extraction is tile most important step in global minimization. Its approache is to identify and extract subexpressions, which are multiple-cubes or single-cubes, common to two or more expressions which can be used to reduce the total number of literals in a Boolean network. Extraction is described as either algebraic or Boolean according to the trade-off between run-time and optimization. Boolean extraction is capable of providing better results, but difficulty in finding common Boolean divisors arises. In this paper, we present a new method for Boolean extraction to remove the difficulty. The key idea is to identify and extract two-cube Boolean subexpression pairs from each expression in a Boolean network. Experimental results show the improvements in the literal counts over the extraction in SIS for some benchmark circuits.

본 논문에서는 여러 개의 출력단을 갖는 논리회로에서 공통식을 찾는 방법을 제안하였다. 각각의 출력단위로 2개의 큐브로 구성된 몫을 찾고, 이 몫들 간의 쌍을 이용해서 부울 공통식을 찾는 방법을 보였다. 실험 결과로 2개의 큐브만을 이용한 공통식 산출만으로 전체 논리회로의 크기를 줄이는 데 효과가 있음을 SIS1.2 결과와 비교하여 보였다.