• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.14-23
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• 2011

In this paper, a 7-bit 2GSPS folding/interpolation A/D Converter(ADC) with a Self-Calibrated Vector Generator is proposed. The ADC structure is based on a folding/interpolation architecture whose folding/interpolation rate is 4 and 8, respectively. A cascaded preprocessing block is not only used in order to drive the high input signal frequency, but the resistive interpolation is also used to reduce the power consumption. Based on a novel self-calibrated vector generator, further, offset errors due to device mismatch, parasitic resistors. and parasitic capacitance can be reduced. The chip has been fabricated with a 1.2V 0.13um 1-poly 7-metal CMOS technology. The effective chip area including the calibration circuit is 2.5$mm^2$. SNDR is about 39.49dB when the input frequency is 9MHz at 2GHz sampling frequency. The SNDR is improved by 3dB with the calibration circuit.

• Journal of information and communication convergence engineering
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• v.9 no.2
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• pp.201-206
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• 2011

FRUC (Frame Rate Up-Conversion) technique needs an effective frame interpolation algorithm using motion information between adjacent neighboring frames. In order to have good visual qualities in the interpolated frames, it is necessary to develop an effective detection and interpolation algorithms for occluded regions. For this aim, this paper proposes an effective occluded region detection algorithm through the adaptive forward and backward motion searches and also by introducing the minimum value of normalized cross-correlation coefficient (NCCC). That is, the proposed scheme looks for the location with the minimum sum of absolute differences (SAD) and this value is compared to that of the location with the maximum value of NCCC based on the statistics of those relations. And, these results are compared with the size of motion vector and then the proposed algorithm decides whether the given block is the occluded region or not. Furthermore, once the occluded regions are classified, then this paper proposes an adaptive interpolation algorithm for occluded regions, which still exist in the merged frame, by using the neighboring pixel information and the available data in the occluded block. Computer simulations show that the proposed algorithm can effectively classify the occluded region, compared to the conventional SAD-based method and the performance of the proposed interpolation algorithm has better PSNR than the conventional algorithms.

• ETRI Journal
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• v.31 no.1
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• pp.80-82
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• 2009

In this letter, a new intra-block coding mode is presented to improve the coding efficiency for band-limited signals. A band-limited block is sub-sampled, and the sub-sampled signal is coded on the basis of the conventional prediction/transform coding. The rest of the samples are reconstructed by interpolation at the decoder side without any side information. Experimental results show that the proposed algorithm achieves coding gains of 2.7% for common intermediate format (CIF), 4.29% for quarter CIF, and 6.39% for 720p60 sequences against the H.264/AVC JM10.2 reference software.

• Journal of IKEEE
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• v.17 no.3
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• pp.275-283
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• 2013

In this paper, a 8bit 10Ms/s CMOS Folding and Interpolation analog-to-digital convertor is proposed. The architecture of the proposed ADC is based on a Folding & Interpolation using FR(Folding Rate)=8, NFB(Number of Folding Block)=4, IR(Interpolation Rate)=8. The proposed ADC adopts a preamplifier sharing method to decrease the number of preamplifier by half comparing to the conventional ones. This chip has been fabricated with a 0.35[um] CMOS technology. The effective chip area is $1.8[mm]{\times}2.11[mm]$ and it consumes 20[mA] at 3.3 power supply with 10[MHz] clock. The INL is -0.57, +0.61 [LSB] and DNL is -0.4, +0.51 [LSB]. The SFDR is 48.9[dB] and SNDR is 47.9[dB](ENOB 7.6b) when the input frequency is 100[kHz] at 10[MHz] conversion rate.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.102-111
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• 2013

In this paper, we proposed a $4{\times}4$ block parallel architecture of interpolation for high-performance H.264/AVC Motion Compensation in 4K UHD($3840{\times}2160$) video real time processing. To improve throughput, we design $4{\times}4$ block parallel interpolation. For supplying the $9{\times}9$ reference data for interpolation, we design 2D cache buffer which consists of the $9{\times}9$ memory arrays. We minimize redundant storage of the reference pixel by applying the Search Area Stripe Reuse scheme(SASR), and implement high-speed plane interpolator with 3-stage pipeline(Horizontal Vertical 1/2 interpolation, Diagonal 1/2 interpolation, 1/4 interpolation). The proposed architecture was simulated in 0.13um standard cell library. The maximum operation frequency is 150MHz. The gate count is 161Kgates. The proposed H.264/AVC Motion Compensation can support 4K UHD at 72 frames per second by running at 150MHz.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.161-163
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• 2005

In this paper, we propose an efficient motion vector recovery algorithm for the new coding standard H.264, which makes use of the Lagrange interpolation formula. In H.264/AVC, a 16$\times$16 macroblock can be divided into different block shapes for motion estimation, and each block has its own motion vector. In the natural video the motion vector is likely to move in the same direction, hence the neighboring motion vectors are correlative. Because the motion vector in H.264 covers smaller area than previous coding standards, the correlation between neighboring motion vectors increases. We can use the Lagrange interpolation formula to constitute a polynomial that describes the motion tendency of motion vectors, and use this polynomial to recover the lost motion vector. The simulation result shows that our algorithm can efficiently improve the visual quality of the corrupted video.

• ETRI Journal
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• v.33 no.2
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• pp.295-298
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• 2011

We propose a motion-compensated frame interpolation method in which an accurate backward/forward motion vector pair (MVP) is estimated based on a parabolic motion model. A reliability measure for an MVP is also proposed to select the most reliable MVP for each interpolated block. The possibility of deformation of bidirectional corresponding blocks is estimated from the selected MVP. Then, each interpolated block is produced by combining corresponding blocks with the weights based on the possibility of deformation. Experimental results show that the proposed method improves PSNR performance by up to 2.8 dB as compared to conventional methods and achieves higher visual quality without annoying blockiness artifacts.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.5
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• pp.421-425
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• 2008

In this research, a 8-bit CMOS 2 stage folding A/D converter is designed, For low power consumption and small chip size, the A/D converter is designed by using folding and interpolation circuit. Folding circuit is composed of the transistor differential pairs which are connected in parallel. It reduces the number of comparator drastically. The analog block composed of folding block, current interpolation circuit, and three stage current comparator is designed with differential-mode for high speed operation. The simulation in a $0.35\;{\mu}m$ CMOS process. shows DNL and SNDR of 0.5LSB and 47 dB at 250 MHz/s sampling frequency.

• Proceedings of the KIEE Conference
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• 2004.07e
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• pp.45-48
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• 2004

This paper presents a new method for finding the Block Pulse series coefficients, deriving the Block Pulse integration operational matrices and generalizing the integration operational matrices which are necessary for the control fields using the Block Pulse functions. In order to apply the Block Pulse function technique to the problems of state estimation or parameter identification more efficiently. it is necessary to find the more exact value of the Block Pulse series coefficients and integral operational matrices.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.927-929
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• 2011

Since DVC (Distributed Video Coding) and FRUC (Frame Rate Up Conversion) techniques need to have an efficient motion compensated frame interpolation algorithms. Conventional works of these applications have mainly focused on the performance improvement of overall system. But, in some applications, it is necessary to evaluate how well the MCI (Motion Compensated Interpolation) frame matches the original frame. For this aim, this paper deals with the modeling methods for evaluating the block-based matching cost. First, several matching criteria, which have already been dealt with the motion compensated frame interpolation, are introduced and then combined to make estimate models for the size of MSE (Mean Square Error) noise of the MCI frame to original one. Through computer simulations, it is shown that the block-based cost evaluation models are tested and can be effectively used for estimating the MSE noise.