• Nuclear Engineering and Technology
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• 제53권11호
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• pp.3790-3797
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• 2021

Although the individual channel readout method can improve the performance of PET detectors with pixelated photo-sensors, such as silicon photomultiplier (SiPM), this method leads to a significant increase in the number of readout channels. In this study, we proposed a novel multiplexing method that could effectively reduce the number of readout channels to reduce system complexity and development cost. The proposed multiplexing circuit was designed to generate bipolar pulses with different zero-crossing points by adjusting the time constant of the high-pass filter connected to each channel of a pixelated photo-sensor. The channel position of the detected gamma-ray was identified by estimating the width between the rising edge and the zero-crossing point of the bipolar pulse. In order to evaluate the performance of the proposed multiplexing circuit, four detector blocks, each consisting of a 4 × 4 array of 3 mm × 3 mm × 20 mm LYSO and a 4 × 4 SiPM array, were constructed. The average energy resolution was 13.2 ± 1.1% for all 64 crystal pixels and each pixel position was accurately identified. A coincidence timing resolution was 580 ± 12 ps. The experimental results indicated that the novel multiplexing method proposed in this study is able to effectively reduce the number of readout channels while maintaining accurate position identification with good energy and timing performance. In addition, it could be useful for the development of PET systems consisting of a large number of pixelated detectors.

• 대한전자공학회논문지SD
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• 제46권1호
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• pp.1-6
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• 2009

고전압 소자에서 스냅백 이후의 유지 전압은 구동전압에 비해 매우 작아서 고전압 MOSFET이 ESD(ElecroStatic Discharge) 파워클램프로 바로 사용될 경우 래치업 문제를 일으킬 수 있다. 본 연구에서는 스택 바이폴라 소자를 이용하여 래치업 문제가 일어나지 않는 구조를 제안하였다. 제안된 구조에서는 유지 전압이 구동전압 보다 높으므로 래치업 문제가 발생하지 않으면서, 기존의 다이오드를 사용한 고전압 파워클램프에 비해 면적이 작으며, 내구성 측면에서 800% 성능향상이 있게 되었다. 제안된 구조는 $0.35{\mu}m$ 60V BCD(Bipolar-CMOS-DMOS) 공정을 사용하여 제작되었으며, TLP(Transmission Line Pulse) 장비로 웨이퍼-레벨 측정을 하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.615-618
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• 2000

A number of studies have recently been made on hardware for a biological neuron f3r application with information processing functions of neural networks. We have been trying to produce hardware from the viewpoint that development of a new hardware neuron model is one of the important problems in the study of neural networks. In this paper, we first discuss the circuit structure of a pulse-type hardware neuron model with the enhancement-mode MOSFETs (E-MOSFETs). And we construct a pulse-type hardware neuron model using I-MOSFETs. As a result, it is shown that our proposed new model can exhibit firing phenomena even if the power supply voltage becomes less than 1.5[V]. So it is verified that our model is profitable for IC.

• 전기학회논문지
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• 제61권5호
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• pp.717-720
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• 2012

Various types of dielectric-barrier-discharge (DBD) devices have been developed for diverse applications for the last decade. In this study, a flat non-thermal DBD micro plasma source under atmospheric pressure has been developed. The flat-panel type plasma is generated by bipolar pulse voltages, and driving gas is air. In this study, the plasma source was investigated with intensified charge coupled device (ICCD) images and Optical Emission Spectroscopy (OES). The micro discharges are generated on the crossed electrodes. For theoretical analysis, 2-dimensional fluid simulation was performed. The plasma source can be driven in air, and thus the operation cost is low and the range of application is wide.

• 한국전기전자재료학회논문지
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• 제22권10호
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• pp.801-807
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• 2009

In this paper, we propose a novel shoot-through protection circuit and pulse generator for half-bridge driver IC. We designed a robust half-bridge driver IC over a variation of processes and power supplies. The proposed circuit is composed a delay circuit using a beta-multiplier reference. The proposed circuit has a lower variation rate of dead time and pulse-width over variation of processes and supply voltages than the conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also, the proposed pulse generator is prevented from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, respectively. The variation ratio is 68%(170 ns) of maximum over variation of processes and supply voltages. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD (Bipolar, CMOS, DMOS) process parameter, and the simulations are carried out using Spectre simulator of Cadence corporation.

• 조명전기설비학회논문지
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• 제19권6호
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• pp.59-66
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• 2005

본 논문은 운방전에 의해서 방사된 전자계 펄스의 특징과 통계에 관한 것으로 LabVIEW 기반의 시변성 자계측정시스템을 구성하였다. 이 자계측정시스템의 주파수대역은 $300[Hz}{\sim}1[MHz]$이고, 응답감도는 2.78[mV/nT]이며, 검출된 자계 파형의 기록에는 수직해상도와 최대기록시간이 각각 12비트와 100[ms]인 데이터취득시스템이 적용하였다. 운방전에 의해서 발생한 전자계 펄스는 파두부분에 하나 또는 둘 이상의 빠른 펄스가 중첩된 양방성 파형으로 나타났다. 운방전의 평균지속시간은 약 $1.05{\pm}0.32[ms]$이었으며, 평균 8개의 양방성 펄스가 발생하였다.

• 전기전자학회논문지
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• 제17권3호
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• pp.267-274
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• 2013

본 논문은 Pulse Frequency Modulation(PFM)/Pulse Width Modulation(PWM) 듀얼 모드 피드백 기반 LED 백라이트 유닛 구동용 LLC 공진 변환 제어 IC 설계에 대한 내용을 제시한다. 공진형 변환기에서 하나의 변압기를 사용하면서, 두 가지 출력 전압을 생성할 수 있는 구조를 제안하였으며, Master 출력은 PFM 방식으로 Slave 출력은 PWM 방식으로 제어하도록 설계 하였다. 2차 측 Master 출력을 제어하기 위해서 파워 스위치 제어 신호의 주파수를 조절하는 PFM 피드백과 2차 측 Slave 출력을 제어하기 위해서 파워 스위치 제어 신호의 펄스 폭을 조절하는 PWM 피드백 회로를 설계하였다. 설계된 IC는 $0.35{\mu}m$ 2 Poly 3 Metal BCD(Bipolar-CMOS-DMOS) 공정을 이용하여 레이아웃 되었으며, 면적은 $2.3mm{\times}2.2mm$ 이다. 또한, 설계한 칩은 5 V 공급 전압으로부터 26 mA의 전류를 소모하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 C
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• pp.1882-1884
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• 2004

In this paper, the waveform parameters of electromagnetic pulses radiated from intracloud discharges were presented. The zero-crossing times and the full pulse widths of the large bipolar electromagnetic pulses due to intracloud discharges are gradually decreased as the stroke proceeds. Also, the electromagnetic pulses tend to be bipolar, with narrow and fast leader pulses superimposed on the initial half cycle. The mean numbers of leader pulses superimposed on the initial half cycle were 1.61${\pm}$0.74 and 1.75${\pm}$0.73 for the positive and negative polarities, respectively.

• 한국전기전자재료학회논문지
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• 제27권11호
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.1189-1192
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• 2008

A new mercury-free flat fluorescent lamp with a single cell having dimension 2.2inches across the diagonal, had been developed which shows a wide, stable operating voltage margin, high luminance and luminous efficacy by adopting the bipolar pulse drive scheme. In this paper, the single cell is expanded into a multi-structured configuration to realize a 32inch sized panel across the diagonal by a simple repetition of the single cells. A driving scheme is proposed for a 2-bit areal selective dimming using dual auxiliary electrodes and bipolar drive scheme.