• 제목/요약/키워드: Bias-stress

검색결과 291건 처리시간 0.041초

냉부하검사(CST)를 활용한 수부냉증의 침치료 효과에 대한 예비 연구 (Effects of Acupuncture on patients with cold hypersensitivity by Cold Stress Test : pilot study)

  • 황덕상;조정훈;이창훈;장준복;김용석;이경섭;이윤재
    • 대한한방체열의학회지
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    • 제5권1호
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    • pp.69-77
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    • 2006
  • Purpose : There are many patients with cold hypersensitivity who want oriental medicine treatment. But there has been no study of acupucture treatment effect on patients. So we examined effects of acupuncture treatment at different acupuncture points and compared results of 1st cold stress test and 2nd cold stress test. Method : 8 patients with hand cold hypersensitivity applied for this study. To rule out an bias, we excluded the patients with skin diseases, spinal nerve disease of cervial spine, external wounds. We measured body temperature with D.I.T.I. We performed cold stress test(CST) by 6 thermographic observation using D.I.T.I ; the 1st was taken after 15 minutes-resting, the 2nd was immediately taken after 1 minute soak in $20^{\circ}C$ water, the 3rd was taken at 10 minutes after the soak, and after a week, the 4th was taken after 15 minutes resting, the 5th was immediately taken after 1 minute soak in $20^{\circ}C$ water, the 6th was taken after 10 minutes with acupunture treatment. There were two groups of patients. First group was acupuncture that performed acupuncture therapy on distal points. Second group was acupuncture that performed acupuncture therapy on proximal points. We compared first CST and second CST recovery rate result. Results : The recovery rate at distal points acupuncture therapy was higher than before of that. but not significantly different. The recovery rate at proximal points acupuncture therapy was significantly higher than before of that. The recovery rate of both the back, the palms, all fingers of after proximal acupuncture therapy was significantly higher than before of that. Conclusions : Acupuncture could be effective therapy method on cold hypersensitivity, especially using proximal acupuncture points could be good at cold hypersensitivity patients. This was pilot study of very small samples, results had limitations. For further results more examine would be needed.

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Effects of Interfacial Dielectric Layers on the Electrical Performance of Top-Gate In-Ga-Zn-Oxide Thin-Film Transistors

  • Cheong, Woo-Seok;Lee, Jeong-Min;Lee, Jong-Ho;KoPark, Sang-Hee;Yoon, Sung-Min;Byun, Chun-Won;Yang, Shin-Hyuk;Chung, Sung-Mook;Cho, Kyoung-Ik;Hwang, Chi-Sun
    • ETRI Journal
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    • 제31권6호
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    • pp.660-666
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    • 2009
  • We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top-gate In-Ga-Zn-oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below $200^{\circ}C$, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as $Si_3N_4$ and $Al_2O_3$, the electrical properties are analyzed. After post-annealing at $200^{\circ}C$ for 1 hour in an $O_2$ ambient, the sub-threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative-bias stress tests on TFTs with a $Si_3N_4$ IDL, the degradation sources are closely related to unstable bond states, such as Si-based broken bonds and hydrogen-based bonds. From constant-current stress tests of $I_d$ = 3 ${\mu}A$, an IGZO-TFT with heat-treated $Si_3N_4$ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge-injection and electron-trapping behavior.

박막 게이트 산화막을 갖는 n-MOSFET에서 SILC 및 Soft Breakdown 열화동안 나타나는 결함 생성 (Trap Generation during SILC and Soft Breakdown Phenomena in n-MOSFET having Thin Gate Oxide Film)

  • 이재성
    • 대한전자공학회논문지SD
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    • 제41권8호
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    • pp.1-8
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    • 2004
  • 두께가 3nm인 게이트 산화막을 사용한 n-MOSFET에 정전압 스트레스를 가하였을 때 관찰되는 SILC 및 soft breakdown 열화 및 이러한 열화가 소자 특성에 미치는 영향에 대해 실험하였다. 열화 현상은 인가되는 게이트 전압의 극성에 따라 그 특성이 다르게 나타났다. 게이트 전압이 (-)일 때 열화는 계면 및 산화막내 전하 결함에 의해 발생되었지만, 게이트 전압이 (+)일 때는 열화는 주로 계면 결함에 의해 발생되었다. 또한 이러한 결함의 생성은 Si-H 결합의 파괴에 의해 발생할 수 있다는 것을 중수소 열처리 및 추가 수소 열처리 실험으로부터 발견하였다. OFF 전류 및 여러 가지 MOSFET의 전기적 특성의 변화는 관찰된 결함 전하(charge-trapping)의 생성과 직접적인 관련이 있다. 그러므로 실험 결과들로부터 게이트 산화막으로 터널링되는 전자나 정공에 의한 Si 및 O의 결합 파괴가 게이트 산화막 열화의 원인이 된다고 판단된다. 이러한 물리적 해석은 기존의 Anode-Hole Injection 모델과 Hydrogen-Released 모델의 내용을 모두 포함하게 된다.

Atomic Layer Deposited ZrxAl1-xOy Film as High κ Gate Insulator for High Performance ZnSnO Thin Film Transistor

  • Li, Jun;Zhou, You-Hang;Zhong, De-Yao;Huang, Chuan-Xin;Huang, Jian;Zhang, Jian-Hua
    • Electronic Materials Letters
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    • 제14권6호
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    • pp.669-677
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    • 2018
  • In this work, the high ${\kappa}$ $Zr_xAl_{1-x}O_y$ films with a different Zr concentration have been deposited by atomic layer deposition, and the effect of Zr concentrations on the structure, chemical composition, surface morphology and dielectric properties of $Zr_xAl_{1-x}O_y$ films is analyzed by Atomic force microscopy, X-ray diffraction, X-ray photoelectron spectroscopy and capacitance-frequency measurement. The effect of Zr concentrations of $Zr_xAl_{1-x}O_y$ gate insulator on the electrical property and stability under negative bias illumination stress (NBIS) or temperature stress (TS) of ZnSnO (ZTO) TFTs is firstly investigated. Under NBIS and TS, the much better stability of ZTO TFTs with $Zr_xAl_{1-x}O_y$ film as a gate insulator is due to the suppression of oxygen vacancy in ZTO channel layer and the decreased trap states originating from the Zr atom permeation at the $ZTO/Zr_xAl_{1-x}O_y$ interface. It provides a new strategy to fabricate the low consumption and high stability ZTO TFTs for application.

출력전류 제어 기능이 향상된 고휘도 LED 구동 IC 설계 (Design of the High Brightness LED Driver IC with Enhanced the Output Current Control Function)

  • 송기남;한석붕
    • 한국전기전자재료학회논문지
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    • 제23권8호
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    • pp.593-600
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    • 2010
  • In this paper, High brightness LED (light-emitting diodes) driver IC (integrated circuit) using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET (metal oxide semiconductor field effect transistor) from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. To confirm the functioning and characteristics of our proposed LED driver IC, we designed a buck converter. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses 1.0 ${\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre (Cadence) simulation.

초등학생 대상의 산림치유 프로그램에 대한 체계적 문헌고찰 (A Systematic Review of Forest Therapy Programs for Elementary School Students)

  • 송민경;방경숙
    • Child Health Nursing Research
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    • 제23권3호
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    • pp.300-311
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    • 2017
  • Purpose: There are many forest and outdoor programs being offered but systematic reviews of effects are lacking. This study was done to identify content, format, and strategies of forest therapy programs for elementary school students. Methods: Literature search using keywords in English and Korean was performed using 6 electronic databases in December 2016. Search participants were elementary school students and interventions conducted in the forest. Seventeen forest therapy studies were selected for evaluation. Risk of Bias Assessment tool for non-randomized study was used for quality assessment. Results: All studies were quasi-experimental designs. Forest therapy programs included various activities in forests such as experience of five senses, meditation in the forest, walking in the forest, ecological play, observation of animals and insects. All studies used psychosocial health variables and forest healing programs had positive effects on sociality, depression, anxiety, self-esteem, stress, aggression, anger, and school adjustment. Limitations of these studies were vague reporting of the study, lack of ethical review and rigorous research designs. Conclusion: Forest therapy for elementary school child can be an effective way to improve psychosocial health. Future studies with rigorous study designs are needed to assess long-term effects of forest therapy on physical and psychosocial health.

P형 짧은 채널(L=1.5 um) 다결정 실리콘 박막 트랜지스터의 오프 상태 스트레스 하에서의 신뢰성 분석 (Positive Shift of Threshold Voltage in short channel (L=$1.5{\mu}m$) P-type poly-Si TFT under Off-State Bias Stress)

  • 이정수;최성환;박상근;한민구
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2009년도 제40회 하계학술대회
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    • pp.1225_1226
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    • 2009
  • 유리 기판 상에 이중 게이트 절연막을 가지는 우수한 특성의 P형 엑시머 레이저 어닐링 (ELA) 다결정 실리콘 박막 트랜지스터를 제작하였다. 그리고 P형 짧은 채널 ELA 다결정 실리콘 박막 트랜지스터의 오프 상태 스트레스 하에서의 전기적 특성을 분석하였다. 스트레스하에서 긴 채널에서의 문턱 전압은 양의 방향으로 거의 이동하지 않는 (${\Delta}V_{TH}$ = 0.116V) 반면, 짧은 채널 박막 트랜지스터의 문턱 전압은 양의 방향으로 상당히 이동 (${\Delta}V_{TH}$ = 2.718V)하는 것을 확인할 수 있었다. 이런 짧은 채널 박막 트랜지스터에서 문턱 전압의 양의 이동은 다결정 실리콘 막과 게이트 산화막 사이의 계면에서의 전자 트랩핑 때문이다. 또한, 박막 트랜지스터의 누설 전류는 오프 상태 스트레스 하에서의 채널 영역의 홀 전하로 인하여 온 전류 수준을 감소시키지 않고 억제될 수 있었다. C-V 측정 결과는 계면의 전자 트랩핑이 드레인 접합 영역부근에서 발생한다는 것을 나타낸다.

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a-Si TFT Integrated Gate Driver Using Multi-thread Driving

  • Jang, Yong-Ho;Yoon, Soo-Young;Park, Kwon-Shik;Kim, Hae-Yeol;Kim, Binn;Chun, Min-Doo;Cho, Hyung-Nyuck;Choi, Seung-Chan;Moon, Tae-Woong;Ryoo, Chang-Il;Cho, Nam-Wook;Jo, Sung-Hak;Kim, Chang-Dong;Chung, In-Jae
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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    • pp.1251-1254
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    • 2006
  • A novel a-Si TFT integrated gate driver circuit using multi-thread driving has been developed. The circuit consists of two independent shift registers alternating between the two mode, "wake" and "sleep". The degradation of the circuit is retarded since the bias stress is removed during the sleep mode. It has been successfully integrated in 14.1-in. XGA LCD Panel, showing enhanced stability.

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Integrated Gate Driver Circuit Using a-Si TFT with AC-Driven Dual Pull-down Structure

  • Jang, Yong-Ho;Yoon, Soo-Young;Kim, Binn;Chun, Min-Doo;Cho, Hyung-Nyuck;Cho, Nam-Wook;Sohn, Choong-Yong;Jo, Sung-Hak;Choi, Seung-Chan;Kim, Chang-Dong;Chung, In-Jae
    • 한국정보디스플레이학회:학술대회논문집
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    • 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.II
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    • pp.944-947
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    • 2005
  • Highly stable gate driver circuit using a-Si TFT has been developed. The circuit has dual-pull down structure, in which bias stress to the TFTs is relieved by alternating applied voltage. The circuit has been successfully integrated in 4-in. QVGA and 14-in. XGA TFT-LCD with a normal a-Si process, which are stable for over 2,000 hours at $60^{\circ}C$. The enhancement of stability of the circuit is attributed to retarded degradation of pull-down TFTs by AC driving.

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출력전류 제어 기능이 향상된 고휘도 LED 구동 IC 설계 (Design of the High Brightness LED Driver IC with Enhanced the Output Current Control Function)

  • 한석붕;송기남
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2010년도 하계학술대회 논문집
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    • pp.9-9
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    • 2010
  • In this paper, High Brightness LED driver IC using new current sensing circuit is proposed. This LED driver IC can provide a constant current with high current precision over a wide input voltage range. The proposed current-sensing circuit is composed of a cascode current sensor and a current comparator with only one reference voltage. This IC minimizes the voltage stress of the MOSFET from the maximum input voltage and has low power consumption and chip area by using simple-structured comparator and minimum bias current. The LED current ripple of the designed IC is in ${\pm}5%$ and a tolerance of the average LED current is lower than 2.43%. This shows much improved feature than the previous method. Also, protections for input voltage and operating temperature are designed to improve the reliability of the designed IC. Designed LED driver IC uses $1{\mu}m$ X-Fab. BiCMOS process parameters and electrical characteristics and functioning are verified by spectre(Cadence) simulation.

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